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#605 Procedural continuous assign or force is only evaluated once
From the standard:
"The right-hand side of a procedural continuous assignment or a force statement can be an expression. This shall be treated just as a continuous assignment; that is, if any variable on the right-hand side of the assignment changes, the assignment shall be reevaluated while the assign or force is in effect."
Icarus Verilog only evaluates the expression once, at the time the assign or force statement is executed.
Test case attached. To run,
iverilog bug.v; a.out
I'm leaving the priority at 5 - although this is incorrect behaviour without a warning, there doesn't seem to be a urgent need for it to be fixed (I only discovered it through trying to thoroughly test my work on pr212317).
Test case exposing bug
This is using a draw_eval_*() which evaluates the expression in thread space, hence only the value at the time the force is called will be used. We have a couple of ways to fix this. One is to create a continuous assignment that is connected to the forced net as needed. This is inefficient in that we have a CA that will always be evaluated whether it is needed or not. Another possibility, but more work, is to build a dynamically created continuous assignment. An enabled CA may also be a possibility. We may want to discuss the possibilities on iverilog-devel.
I was thinking about this a bit over the weekend. If you build the force/assign value as a continuous assign and then use a single variable in the force/assign this will work as expected. So you can use the following code to get things to work.
wire [7:0] tmp = a + b;
and then use tmp instead of a + b in the continuous assign.
I've now added a tgt-vvp sorry message to warn the user about this bug.