Sigrity X OptimizePI
To ensure you get high performance at a system and component level, while at the same time saving between 15% and 50% in decoupling capacitor (decap) costs, Cadence® Sigrity X OptimizePI™ technology does a complete AC frequency analysis of boards and IC packages. Supporting both pre- and post-layout studies, it quickly pinpoints the best decap selections and placement locations to meet your power-delivery network (PDN) needs at the lowest possible cost. Sigrity X OptimizePI technology is built on proven Cadence hybrid electromagnetic circuit analysis technology in combination with the unique Sigrity optimization engine to help you quickly pinpoint the best possible decap selections and placement locations.
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Sigrity X Platform
Step into the future with Sigrity X Platform – where innovation meets optimization. Unlock the key to flawless signal and power integrity in your PCB and IC package designs, and leap far beyond the current limits of signal integrity (SI)/power integrity (PI) technology. Imagine effortlessly navigating the complexities of electronic design, and not just meeting, but shattering your time-to-market targets with precision and ease.
With Sigrity X, you're not just working with another tool; you're unlocking seamless in-design analysis synergy within the Allegro X PCB and IC Package platforms. Dive into a comprehensive suite of SI/PI analysis, in-design interconnect modeling, and PDN analysis tools designed to supercharge your performance, ensuring your projects not only meet but exceed deadlines and budgets.
Harness the power of the Sigrity X Platform for flawless performance and reliability success in your next design.
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Siemens Aprisa
Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC. Aprisa digital implementation is an RTL2GDSII solution that offers complete synthesis and place-and-route functionality for top-level hierarchical designs and block-level implementation. It's tape-out quality correlation with signoff tools, both for STA timing and DRC, reduces design closure and ensures optimal performance, power, and area (PPA). Aprisa delivers optimal PPA out-of-the-box. This helps physical designers reduce the effort at each step of the place-and-route flow and achieve faster time-to-market Unified architecture and common analysis engines ensure excellent timing and DRC correlation between implementation steps and with signoff tools, greatly reducing the number of flow iterations and ECOs.
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Oasys-RTL
Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities. Oasys-RTL provides better quality results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time. The power-aware synthesis capabilities include support for multi-threshold libraries, automatic clock gating, and UPF-based multi-VDD flow. During synthesis, Oasys-RTL inserts all the appropriate level shifters, isolation cells, and retention registers depending on the power intent as defined in the UPF. Oasys-RTL can create a floorplan directly from the design RTL using design dataflow and timing, power, area, and congestion constraints. It considers regions, fences, blockages, and other physical guidance using the advanced floorplan editing tools and automatically places macros, pins, and pads.
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