Audience
IC professionals in need of a tool to optimize their designs and improve their RTL synthesis operations
About Oasys-RTL
Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities. Oasys-RTL provides better quality results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time. The power-aware synthesis capabilities include support for multi-threshold libraries, automatic clock gating, and UPF-based multi-VDD flow. During synthesis, Oasys-RTL inserts all the appropriate level shifters, isolation cells, and retention registers depending on the power intent as defined in the UPF. Oasys-RTL can create a floorplan directly from the design RTL using design dataflow and timing, power, area, and congestion constraints. It considers regions, fences, blockages, and other physical guidance using the advanced floorplan editing tools and automatically places macros, pins, and pads.
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Company Information
Siemens
Founded: 1847
United States
eda.sw.siemens.com/en-US/ic/oasys-rtl/
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