Audience
Enterprises interested in an electrostatic discharge simulation software to plan, verify and sign-off IP and full-chip SoC designs
About Ansys PathFinder
Ansys PathFinder-SC is a high-capacity solution to help you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). Ansys PathFinder-SC identifies and isolates the root causes of design issues that can cause chip failure from charged-device model (CDM), human body model (HBM), or other ESD events. It’s high-capacity, cloud-native architecture can enlist thousands of compute cores for fast full-chip turnaround. PathFinder-SC is certified by major foundries for current density checks and ESD sign-off. PathFinder-SC’s integrated data modeling, extraction and transient simulation engine is an end-to end solution for ESD verification. The single-pass use model reads industry-standard design formats, sets up ESD rules, extracts the RCs for the power network, and performs ESD simulations to analyze root causes and provide fix and optimization feedback, all within a single tool.
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