Audience
Companies looking for a Variability-aware SoC path timing and clock tree analysis software
About Ansys Path FX
Ansys Path FX allows you to calculate timing with variation on a full SoC, without taking any shortcuts. Its unique cell modeling delivers SPICE accuracy timing for any voltage or variation condition with a single library. Path FX has a fully threaded and distributed architecture, with the ability to scale to thousands of CPUs. Ansys Path FX’s path-based timing analysis has the technology to account for all critical contributors to delay and constraints across multiple process, voltage, temperature corners and scenarios. It can also automatically identify and simulate every clock path in your design. Two of the biggest challenges facing successful chip design today are limiting the power consumption through lower supply voltages and managing the complexity of advanced silicon processes at 7nm and below.
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Company Information
Ansys
Founded: 1970
United States
www.ansys.com/products/semiconductors/ansys-path-fx
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Ansys VeloceRF
Ansys VeloceRF shortens the design cycle by greatly reducing the time it takes to synthesize and model complex spiral devices and T-lines. It takes only a few seconds to compile an inductor or transformer geometry, and just a couple of minutes to model and analyze it. It integrates with leading EDA platforms, instantiating ready-to-tape-out layouts. Ansys VeloceRF allows you to synthesize devices with tight packing of multiple devices and lines for an optimized silicon floorplan. Analysis of the coupling among any number of inductive devices before detailed layout will reduce design size and reduce or eliminate guard rings. Inductor size as well as inductor-to-inductor crosstalk can impact the die size. Ansys VeloceRF helps you design smaller devices through the use of optimization criteria and geometry constraints. In addition, it calculates coupling among any number of inductors to better optimize silicon real estate and to optimize inductors in circuit context.
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PathWave EM Design
Electromagnetic (EM) simulation brings you insight before physical prototyping. Customize EM simulations for speed and accuracy. Integrate EM analysis with your circuit simulations. EM simulations can take hours to run. Shorten your import and export time by integrating your EM simulation software with PathWave Circuit Design software. Integrate EM analysis with circuit simulations to maximize efficiency. 3D EM solid modeling environment for creating arbitrary 3D objects and importing existing 3D models from other CAD environments. Prerequisite for preparing a 3D geometry for 3DEM simulation by defining ports, boundary conditions and material properties. 3D EM solid modeling environment and Finite Difference Time Domain (FDTD) simulator. Compliance testing for Specific Absorption Rate (SAR) and Hearing Aid Compatibility (HAC).
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Ansys RedHawk-SC
Ansys RedHawk-SC is the industry’s trusted gold standard voltage drop and electromigration multiphysics sign-off solution for digital designs. Its powerful analytics quickly identify any weaknesses and allow what-if explorations to optimize power and performance. Redhawk-SC’s cloud-based architecture gives it the speed and capacity to handle full-chip analysis. Signoff accuracy is certified by all major foundries for all finFET nodes, down to 3nm. Ansys RedHawk-SC enables robust, low-power digital designs without performance loss thanks to advanced power analytics that give designers comprehensive techniques to detect and correct dynamic voltage drop. Ansys RedHawk-SC’s trusted multiphysics signoff analysis is a powerful way to reduce project and technology risk. RedHawk’s algorithms are certified accurate by all major foundries for all finFET processes and are proven in thousands of tapeouts.
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Ansys PathFinder
Ansys PathFinder-SC is a high-capacity solution to help you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). Ansys PathFinder-SC identifies and isolates the root causes of design issues that can cause chip failure from charged-device model (CDM), human body model (HBM), or other ESD events. It’s high-capacity, cloud-native architecture can enlist thousands of compute cores for fast full-chip turnaround. PathFinder-SC is certified by major foundries for current density checks and ESD sign-off. PathFinder-SC’s integrated data modeling, extraction and transient simulation engine is an end-to end solution for ESD verification. The single-pass use model reads industry-standard design formats, sets up ESD rules, extracts the RCs for the power network, and performs ESD simulations to analyze root causes and provide fix and optimization feedback, all within a single tool.
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