VICE Files

2018-04-24 [r34721] fix envelope bugs shown by testprogs/SID/env_test/

2017-03-14 [r32988] 6581 oscillator top bit behavior fix
2017-03-13 [r32987] fix 8580 filters
2017-03-13 [r32986] fix envelope timing issues
2017-03-13 [r32985] 8580 filter bias range
2017-01-05 [r32605] hack to fix integer overflow
2017-01-01 [r32587] SID noise writeback improvement

2016-12-31 [r32579] filter bias tweak value fix
2016-12-31 [r32578] SID envelope generator improvements
2016-12-31 [r32576] SID 8580 filter improvements
2016-08-16 [r31615] (hopefully) fix the noise writeback and lfsr details.
2016-08-12 [r31587] As the OSC3 register is sampled in the first clock phase 
                    while the tri/saw output is latched on the second phase the 
                    delay will be noticed only on OSC3 read, since we produce 
                    the waveform output when phi2 is high
2016-08-10 [r31571] register writes are NOT delayed by a cycle on 8580 - instead 
                    the perceived delay is caused by a half cycle delay in the 
                    sawtooth/triangle output
2016-08-09 [r31558] The oscillator's value is 55555 at power up (all bits are 1 
                    but odd ones are stored inverted) and is not changed on 
                    reset.
2016-08-08 [r31541] The effect of the top bit of the ring modulating voice was 
                    inverted
2016-08-08 [r31538] Reading from a write-only or non-existing register returns 
                    the value left on the internal data bus, which is refreshed 
                    not only on writes but also on valid reads from the read-
                    only registers

2015-12-25 [r30331] fix bus TTL
2015-12-24 [r30329] add hard clipping to 8580 mixer output