verilog compiler Files

README FIRST - VERILOG COMPILER - AUG 22 2009

The Verilog Compiler was part of a suite of programs developed for
Pittsburgh Simulation in the 2002 to 2005 timeframe for a hardware simulation
accelerator called the V400. It has been released to the public domamin by the
CEO in part because the company no longer exists.

The verilog compiler can stand alone and be useful
by itself. If nothing else it is useful to see how JavaCC, the Purdue Java Tree Builder,
and a graph package may be used to compile a complex language like verilog.

The "Compiler Manual.pdf" file provides an overview of the many features of the compiler
and other programs in the suite. Ignore everything except the verilog compiler
as they were very specific to the V400 hardware. The manual refers to an example
called CKT_TOP which is half a dozen .v modules. This example circuit and the cell
library it used was owned by a client and I am not sure it can be publicly released yet.

The compiler uses a cell library which consists of a collection of .v files, little modules,
describing each cell in the verilog language. The compiler needs a cell_lib.txt file
which maps the cell name to pin names. The other fields may all be 0000 because they are not
used by the compiler. So in fact, it may be necessary to fake up a cell_lib.txt file
to compile anything since in the initial release we are unable to provide the clients
cell library or test example.

Source code and building the compiler:

The compiler was originally written using JDK1.4 so it uses some old ways of looping and
doing enumerations. The source forge released version has been built ok in Netbeans 6.5
with JDK 1.6. There are two external libraries/jar files that are used. The gnu getopt for parsing
command line arguments and the Generic Graph Package from RPI that was written in 1998.
http://www.cs.rpi.edu/research/groups/pb/jgb/index.html

The verilogx/src/syntaxtree and visitor directories contain source code generated by the
Purdue Java Tree Builder from the grammer verilog1.jj in the src directory. 
http://compilers.cs.ucla.edu/jtb/jtb-2003/

You will have to read the documentation for the JTB to understand how crucial it is to
the verilog compiler and how the visitor pattern works.

The beauty of this approch is that semantic actions are not mixed into the grammar
as they are in yacc.y files for the YACC parser generator. 

Charlie Havener
http://www.cdhconsult.com