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Ready for HFT.zip (522.7 MB)
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| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| IP SREC bootloader works.tar.gz | 2021-03-09 | 422.2 MB | |
| IP SREC bootloader works.zip | 2021-03-09 | 427.9 MB | |
| README.md | 2021-03-09 | 560 Bytes | |
| Totals: 3 Items | 850.1 MB | 0 | |
With this pre-release the system DOCS / HW / FPGA runs up into the application code using RTOS. Both, the external PLL setup and the SREC-bootloader (loads @ 0x00800000) are done in FPGA logic and are therefore very fast. The time to run the application is abt. 1 second for all (FPGA configuration, PLL setup, SREC memory copy and start).
What is included in the App: - RTOS - Transmitting a UFBmod packet every few seconds - Receiving a packet (untested at that moment)
This is a pre-release and for end-users not acceptable yet.
Cheers, Uli.