SpinalHDL Files

What's Changed

• Fix for Issue 1736 VHDL assertions without a report clause. by @jtredux in https://github.com/SpinalHDL/SpinalHDL/pull/1808
• Wrap extrema by @thajohns in https://github.com/SpinalHDL/SpinalHDL/pull/1807
• Add APLIC and IMSIC device support by @inochisa in https://github.com/SpinalHDL/SpinalHDL/pull/1811
• fix the path pattern of generating vcd on msys2 environment. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1810
• Util/Counter: Adding 2 new object overloads for creation based on a t… by @mrberman87 in https://github.com/SpinalHDL/SpinalHDL/pull/1797
• Implement automatic initial reset and signal analysis in Verilator ba… by @jaynerlin in https://github.com/SpinalHDL/SpinalHDL/pull/1806
• lib: misc: aia: APlicSource: fix wrong mode access when update sourcecfg by @inochisa in https://github.com/SpinalHDL/SpinalHDL/pull/1812
• VCS Backend: handle hex memory files by @Nik-Sch in https://github.com/SpinalHDL/SpinalHDL/pull/1816
• Add Workaround for RAM with init values in sim by @g0t00 in https://github.com/SpinalHDL/SpinalHDL/pull/1777
• Nested PackedWordBundle unpack fix by @dokleina in https://github.com/SpinalHDL/SpinalHDL/pull/1821
• AxiLite4Master: do not allow more than 1 outstanding transaction by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1822
• Add random isolation test suites for SpinalHDL and Verilator by @jaynerlin in https://github.com/SpinalHDL/SpinalHDL/pull/1787
• Mark unused data line as dont care; prevents unassigned errors in certain test modes by @jdavidberger in https://github.com/SpinalHDL/SpinalHDL/pull/1824
• Add CascadedInterruptCtrlFiber to support dynamic interrupt delegation by @inochisa in https://github.com/SpinalHDL/SpinalHDL/pull/1815
• AFix resize() bug by @thajohns in https://github.com/SpinalHDL/SpinalHDL/pull/1801
• Add tester for APlic and fix some bugs by @looongbin in https://github.com/SpinalHDL/SpinalHDL/pull/1828
• fix typo by @thajohns in https://github.com/SpinalHDL/SpinalHDL/pull/1832
• add AFix contructors from width and resolution by @thajohns in https://github.com/SpinalHDL/SpinalHDL/pull/1800
• add simSetAll method for simulation. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1837
• Fix asReversedBits by @thajohns in https://github.com/SpinalHDL/SpinalHDL/pull/1835
• [#1839] workaround by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1841
• lib: spinal: bus: wishbone: Fix Output to Slave Assignment by @dnltz in https://github.com/SpinalHDL/SpinalHDL/pull/1847
• add Clip utility by @facebreeze in https://github.com/SpinalHDL/SpinalHDL/pull/1849
• Regif Optimize and bug Fix by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1836
• Replace hardcoded 32 with width parameter in extendedMantissa by @jooyeon111 in https://github.com/SpinalHDL/SpinalHDL/pull/1855
• Fix spelling mistakes by @Tectu in https://github.com/SpinalHDL/SpinalHDL/pull/1861
• Add clear input signal to StreamShiftChain by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1867
• Fix Fragment.reduce accumulator not initialized by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1866
• Fix SInt exclusion checking when using a negative number literal by @inochisa in https://github.com/SpinalHDL/SpinalHDL/pull/1863
• refine StreamArbiter to improve RTL quality. by @facebreeze in https://github.com/SpinalHDL/SpinalHDL/pull/1856
• refine StreamFork when portCount = 1 by @facebreeze in https://github.com/SpinalHDL/SpinalHDL/pull/1869
• feat: optionally include the call-site location (file and line) in the report output by @pluveto in https://github.com/SpinalHDL/SpinalHDL/pull/1873
• Add Bcd data type by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1870
• add names for StreamWidthAdapter to improve RTL code readability. by @facebreeze in https://github.com/SpinalHDL/SpinalHDL/pull/1876
• Bump mill to version 1.1.0 by @inochisa in https://github.com/SpinalHDL/SpinalHDL/pull/1862
• Enhance the plugin system by @Aqwyh123 in https://github.com/SpinalHDL/SpinalHDL/pull/1872
• remove unused signals of FSM to improve RTL code quality by @facebreeze in https://github.com/SpinalHDL/SpinalHDL/pull/1878

New Contributors

• @jtredux made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1808
• @inochisa made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1811
• @looongbin made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1828
• @jooyeon111 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1855
• @Aqwyh123 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1872

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.13.0...v1.14.0