HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

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License

GNU General Public License version 2.0 (GPLv2)

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  • xtofb Posted 2013-07-20
    This is AWESOME indeed. But it is hard to find and it really could use some documentation...
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Additional Project Details

Operating Systems

Linux

User Interface

Qt

Programming Language

Perl, C++, VHDL/Verilog, Yacc

Registered

2006-07-12
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