Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai

Project Samples

circuit diagram D trigget synthesizedby by Synplify Peripheral circuit of single chip synthesize by Synplify 4-bit-couter simulation synthesized 74138' HDL generated by Scicos HDL by Synplify

Project Activity

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Categories

Chat, Email, Window Managers

License

GNU Library or Lesser General Public License version 2.0 (LGPLv2)

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Additional Project Details

Operating Systems

Linux, FreeBSD, Windows

Languages

English, Chinese (Simplified)

Intended Audience

Healthcare Industry, Science/Research, Education, Telecommunications Industry, Developers

User Interface

Tk

Programming Language

C, Tcl, VHDL/Verilog, IDL

Related Categories

C Chat Software, C Email Software, C Window Managers, Tcl Chat Software, Tcl Email Software, Tcl Window Managers, VHDL/Verilog Chat Software, VHDL/Verilog Email Software, VHDL/Verilog Window Managers, IDL Chat Software, IDL Email Software, IDL Window Managers

Registered

2006-07-25
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