Orchestra, a SoC Generator download

The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.

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License

GNU Library or Lesser General Public License version 2.0 (LGPLv2), GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Operating Systems

Linux, Windows

Intended Audience

Developers, Other Audience

User Interface

Console/Terminal

Programming Language

Python, VHDL/Verilog

Related Categories

Python Electronic Design Automation (EDA) Software, VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2008-03-13

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