Download Latest Version
monsputer-20170101.tar.bz2 (6.0 MB)
Get an email when there's a new version of Monsputer project
| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| ANTIMER5.PLD | 2024-06-01 | 7.8 kB | |
| Z80SERIAL.PLD | 2024-05-19 | 10.6 kB | |
| Z80_DRAM.PLD | 2024-04-28 | 3.6 kB | |
| FLASHRAM.PLD | 2024-04-28 | 1.4 kB | |
| Z80glue.pld | 2024-04-28 | 3.4 kB | |
| README.txt | 2024-04-28 | 995 Bytes | |
| SPI doc.txt | 2022-07-29 | 2.5 kB | |
| Z80probe.pld | 2018-05-20 | 1.6 kB | |
| Parallel.pld | 2016-06-04 | 2.0 kB | |
| revers.pld | 2016-06-04 | 1.4 kB | |
| Z80INT.PLD | 2016-06-04 | 3.2 kB | |
| Totals: 11 Items | 38.7 kB | 0 | |
Z80probe.pld Bus display and single stepping circuit The bus display uses a 48-bit shift register read by an Atmel ATmega328p connected to a PC through a serial port Z80SERIAL.PLD On the CAN I2C Serial SPI card: Address decoding for several chips implements an SPI interface implements a 16 level interrupt controller Parallel.pld On the CAN I2C Serial SPI card: Implement a standard parallel port in compatibility mode It can input bytes from the data lines. ANTIMER5.PLD On the Analog Timer card: Address decoding for several chips implements an SPI interface revers.pld connects to a 8255 port in the bidirectional mode Z80_DRAM.PLD On the memory expension card: implements a DRAM controler. It adds an 8th bit to the refresh counter An external delay line is needed to generate the multiplexing signals Z80glue.pld address decoding. This version is for the cleaned up circuit of the Z80 CPU Z80INT.PLD implements a small interrupt controller (bonus)