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20240119_LimeSDR-Mini-v2_GW-main_share.zip (19.4 MB)
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| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| GW2p7_lms7_trx_impl1_GPIOHACK.bit | 2024-12-18 | 1.1 MB | |
| 20240119_LimeSDR-Mini-v2_GW-main_share.zip | 2024-01-22 | 19.4 MB | |
| __lime_mini2p0_gateware_instruction.pdf | 2024-01-22 | 639.7 kB | |
| lms7_trx_impl1_GPIOHACK.bit | 2024-01-22 | 1.1 MB | |
| lms7_trx_impl1_unchanged.bit | 2024-01-22 | 1.1 MB | |
| readme.txt | 2024-01-22 | 945 Bytes | |
| Totals: 6 Items | 23.3 MB | 0 | |
Gatewares for LimeSDR Mini2.0 with GPIO modification Tested with the following device: LimeSDR-Mini_v2 FW:10 HW:5 Protocol:1 GW:2.6 Ref Clk: 40.00 MHz therefore using gateware 2.6 that was up to date on January 2024 LimeSuite had version 23.11 Aside from technicalities because Diamond Lattice is used for gateware compilation (and needs to be installed at first hand...), the Mini2.0 is having a conceptually similar gateware than the LimeSDR USB. There is some very crude information on the compulation process in lime_mini2p0_gateware_instruction.pdf and where changes were made Since FPGA_GPIO[4 to 7] are used in connection with the newly added status LEDs for RX and TX activitiy indication with the mini2.0, the four extra bits have been put to FPGA_GPIO[0 to 3]. These are different pins on J3 than those used previously in mini1.0 and USB versions. So one needs to take some care there on pin assignment among different GPIO mods.