/*===========================================================================*/
For feedback, comments, or questions, please contact Xi Chen (chexi@umich.edu)
and Zyad Hassan (zyad.hassan@colorado.edu).
/*===========================================================================*/
Summary
ISAC2 is a static and dynamic multiscale thermal analysis program for
integrated circuits. Refer to the following research papers for a description of
ISAC2:
X. Chen, R. P. Dick, and L. Shang, "Properties of and Improvements to
Time-Domain Dynamic Thermal Analysis Algorithms", in Proc. Design,
Automation, & Test in Europe, Mar. 2010.
N. Allec, Z. Hassan, L. Shang, R. P. Dick, and R. Yang,"ThermalScope:
Multi-scale thermal analysis for nanometer-scale integrated circuits",
in Proc. IEEE/ACM International Conference on Computer-Aided Design,
Nov. 2008.
The following people have contributed to the development of ISAC2:
Nicholas Allec
Xi Chen
Robert Dick
Zhenyu (Peter) Gu
Zyad Hassan
Li Shang
Yonghong Yang
Changyun Zhu
ISAC2 is built on ISAC, a static and dynamic thermal analysis software
package. The initial version of ISAC was described in the following research
paper:
Y. Yang, Z. Gu, C. Zhu, L. Shang, and R. P. Dick, "Adaptive Chip-Package
Thermal Analysis for Synthesis and Design," Proc. Conf. on Design,
Automation, and Test in Europe, March 2006.
ISAC2 consists of a device temperature solver, as well as a
chip-package analysis tool. Together, the thermal profile of a chip can be
computed down to the device-level, taking into account the nanoscale thermal
effects, such as the ballistic phonon effect. In the following, the device
solver, and the chip-package analysis tool will be described.
ISAC2 needs the AMD Core Math Library (ACML) to be available. ACML can
be downloaded from:
http://developer.amd.com/cpu/Libraries/acml/Pages/default.aspx
** The Makefile assumes that ACML is installed it in /usr/local/acml, so please
specify this as the installation directory when prompted. Alternatively, you
can modify the path in the Makefile to point to the correct directory where
ACML is installed.
/*===========================================================================*/
Device solver
The device solver is built upon the Boltzmann Transport Equation (BTE) model,
which has been shown in the literature that it can model the nanoscale thermal
effects that are present in deeply scaled devices. This is contrary to the
Fourier model which is widely used in chip-package thermal analysis tools,
which can model heat transfer, only down to certain length scales. The device
solver can be used to perform steady-state or transient thermal analysis of
single devices taking into account nanoscale thermal effects.
ISAC2 allows using the device solver results in conjunction with
chip-package analysis to report accurate temperatures down to the device level.
The accurate temperature information can be used to carry out leakage power
analysis, reliability analysis, timing analysis, and so on.
Because the device solver is relatively slow, ISAC2 provides the
capability of generating a look-up table with the results that can be
consulted during the chip-package analysis. This allows carrying out the device
analysis once per device type, rather than once per device instance.
The device solver can also be used alone for generating the temperature
profiles of single devices, which can be used, for instance, in studying the
effect of device geometry, materials and power consumption on the device's
temperature profile.
/*===========================================================================*/
Using the device solver
/* Step 1 */
/* Create the device structure from the input file. The input file contains the
* device geometric information, material properties, power consumption and
* solver options. The structure of the device file is described towards the
* end of this README file. */
Device_structure device;
device.input("input_file_name");
/* Step 2 */
/* Solve the device structure */
device.solve();
/* Step 3 */
/* Generate the output from the solver. If the results are to be used for
* full-chip analysis, then a look-up table can be generated as in step 3.a.
* Otherwise, if the whole temperature profile of the device needs to be
* examined, it can be printed out as shown in step 3.b. */
/* Step 3.a */
/* Generate the look-up table. The look-up table can be later used in full-chip
* analysis. */
device.generateLUT("LUT_file_name");
/* Step 3.b */
/* If desired, the program can generate the temperature profile of the whole
* device. This can be used to study the effect of device geometry and
* materials on its temperature profile.
device.output("output_file_name");
/*===========================================================================*/
Performing Multi-scale Thermal Analysis
The steps for performing full-chip multi-scale thermal analysis are described
next.
/* Step 1.a */
/* Create an ISAC object consisting of the chip information, boundary
* conditions and the floorplan. The chip-package configuration and the
* floorplan can be specified in one of two ways, either inside the program, or
* using input files. Specifying them using input files will be described in
* Step 1.b. For specifying the chip-package configuration inside the program,
* a vector of Layer_type should be created and filled with data as follows: */
vector<Layer_type> chipPkg;
chipPkg.resize(3);
chipPkg[0].property = POWER_;
chipPkg[0].size[X_] = 16.3E-3;
chipPkg[0].size[Y_] = 16.3E-3;
chipPkg[0].size[Z_] = 0.0;
chipPkg[0].cond = 142.3;
chipPkg[0].cap = 1.66E6;
chipPkg[1].property = MATERIAL_;
chipPkg[1].size[X_] = 16.3E-3;
chipPkg[1].size[Y_] = 16.3E-3;
chipPkg[1].size[Z_] = 0.725E-3;
chipPkg[1].cond = 142.3;
chipPkg[1].cap = 1.66E6;
chipPkg[1].par[X_] = 16;
chipPkg[1].par[Y_] = 16;
chipPkg[1].par[Z_] = 8;
chipPkg[2].property = MATERIAL_;
chipPkg[2].size[X_] = 34.0E-3;
chipPkg[2].size[Y_] = 34.0E-3;
chipPkg[2].size[Z_] = 2E-3;
chipPkg[2].cond = 237;
chipPkg[2].cap = 2.43E6;
chipPkg[2].par[X_] = 16;
chipPkg[2].par[Y_] = 16;
chipPkg[2].par[Z_] = 4;
/* where the "property" member specifies the layer type (either POWER_,
* MATERIAL_, or INTERFACE_ for a power layer, a material layer, or an
* interface layer respectively). The "size" member specifies the size of the
* layer, the "cond" and "cap" members specify the thermal conductivity and the
* heat capacity of the layer material, and "par" specifies the initial grid
* for this layer. The above example is of a chip that has a single layer, and
* a heat sink, with the active (power) layer on top of the material layer. The
* material layer is of dimensions 16.3mmx16.33mmx725um, and has a thermal
* conductivity of 142.3 W/m-K and a heat capacity of 1.6e6 J/(m^3-K). The
* initial partition is chosen to be 16x16x8. Th heat sink has dimensions of
* 34mmx34mmx2mm, and has a thermal conductivity of 237 W/m-K, and a heat
* capacity of 2.43E6 J/(m^3-K). The initial partition is chosen to be 16x16x4.
* For specifying the floorplan, a vector of FlrplanElt_type should be created
* and filled with data as follows: */
vector<FlrplanElt_type> flrplan;
flrplan.resize(4);
frplan[0].x_min = -8.15E-3;
frplan[0].x_max = 0.0;
frplan[0].y_min = -8.15E-3;
frplan[0].y_max = 0.0;
frplan[1].x_min = -8.15E-3;
frplan[1].x_max = 0.0;
frplan[1].y_min = 0.0;
frplan[1].y_max = 8.15E-3;
frplan[2].x_min = 0.0;
frplan[2].x_max = 8.15E-3;
frplan[2].y_min = -8.15E-3;
frplan[2].y_max = 0.0;
frplan[3].x_min = 0.0;
frplan[3].x_max = 8.15E-3;
frplan[3].y_min = 0.0;
frplan[3].y_max = 8.15E-3;
/* The above floorplan has 4 blocks of equal size. Note that the point (0.0,
* 0.0) is always the center of the chip. The boundary conditions are specified
* via the chip ambient temperature (in Kelvin), the ambient resistivity due to
* convection (in K-m^2/W), and the ambient heat capacitivity between the
* heatsink and the environment (in J/(m^2-K)). In this example, we will assume
* a 318.15 Kelvin ambient temperature, an ambient resistivity of 7.43E-4
* K-m^2/W, and a heat capacitivity of 1.0 J/(m^2-K). */
Boundary bond(328.15, 7.43E-4, 1.0);
/* Finally the ISAC object can be created as follows: */
ChipPkg_type chip3D;
ISAC isac;
isac = form_isac(chip3D, chipPkg, flrplan, bond);
/* Step 1.b */
/* Or, if the user wishes to specify the chip-package configuration and the
* floorplan via input files, the following overloaded function should be used
* instead: */
isac = form_isac(chip3D, "chip_filename", "floorplan_filename", bond);
/* where "chip_filename" is the name of the file containing the chip-package
* configuration, and "floorplan_filename" is the name of the file containing
* the chip floorplan. The structure of those 2 files will be described later.
* */
/* Step 1.c */
/* The tool also allows creating layers that have a non-homogeneous thermal
* conductivity and/or a non-homogeneous heat capacity. This is useful for
* example in the case of layers containing vias. The tool allows specifying a
* heterogeneous conductivity/heat capacity for any of the layers. Defining a
* heterogeneous conductivity (or heat capacity) is done by specifying the bulk
* conductivity, i.e. the dominant conductivity throughout the layer, and then
* specifying the areas that have a different conductivity. The method for
* specifying that differs depending on whether the user chooses Step 1.a or
* Step 1.b. If the user chooses Step 1.a, specifying a non-homogeneous
* conductivity for a layer can be done as shown in the next example: */
chipPkg[1].property = MATERIAL_;
chipPkg[1].size[X_] = 16.3E-3;
chipPkg[1].size[Y_] = 16.3E-3;
chipPkg[1].size[Z_] = 0.725E-3;
chipPkg[1].cond = 142.3;
chipPkg[1].cond_map.resize(3);
chipPkg[1].cond_map[0].center[0] = 0.0;
chipPkg[1].cond_map[0].center[1] = 0.0;
chipPkg[1].cond_map[0].size[0] = 1E-6;
chipPkg[1].cond_map[0].size[1] = 2E-6;
chipPkg[1].cond_map[0].value = 50.0;
chipPkg[1].cond_map[1].center[0] = 1E-3;
chipPkg[1].cond_map[1].center[1] = -2E-3;
chipPkg[1].cond_map[1].size[0] = 3E-6;
chipPkg[1].cond_map[1].size[1] = 4E-6;
chipPkg[1].cond_map[1].value = 70.0;
chipPkg[1].cond_map[2].center[0] = -3E-3;
chipPkg[1].cond_map[2].center[1] = -4E-3;
chipPkg[1].cond_map[2].size[0] = 5E-6;
chipPkg[1].cond_map[2].size[1] = 6E-6;
chipPkg[1].cond_map[2].value = 90.0;
chipPkg[1].cap = 1.66E6;
chipPkg[1].par[X_] = 16;
chipPkg[1].par[Y_] = 16;
chipPkg[1].par[Z_] = 8;
/* The layer specified above is similar to the one specified in Step 1.a,
* except that it has a non-homogeneous thermal conductivity. The bulk
* conductivity throughout the layer is 142.3 (define by "chipPkg[1].cond =
* 142.3;"), and the layer contains 3 areas with a different conductivity. The
* first area is centered at (0.0, 0.0), i.e. the center of the chip, and has a
* size of 1umx2um. The thermal conductivity in this area is 50.0. Similarly,
* the two other areas are centered at (1E-3, -2E-3) and (-3E-3, -4E-3), have
* sizes of 3umx4um and 5umx6um and values of 70.0 and 90.0 respectively. A
* heterogeneous heat capacity can be specified in a similar way, replacing
* "cond" with "cap". Alternatively, if the user is using input files for
* specifying the chip-package configuration (i.e. through Step 1.b), a
* non-homogeneous conductivity/heat capacity can be indicated by setting its
* value in the chip-file to -1, and giving a filename that contains the
* conductivity/heat capacity map for that layer. This is explained in the next
* "Chip File" section */
/* Step 2 */
/* Specify the power profile. Create a two-dimensional vector. The first
* dimension specifies the power layer, and the second is the block index. The
* number of blocks must be the same as the floorplan file, and their order
* will be the same. */
vector<vector<double> > power;
power.resize(1);
power[0].resize(4);
power[0][0] = 1.0;
power[0][1] = 2.0;
power[0][2] = 3.0;
power[0][3] = 4.0;
/* Step 3 */
/* Perform thermal analysis. There are several functions that can be used for
* thermal analysis. All functions return a vector of Element_type, which
* consists of the element location, size, and its temperature. The
* functions are:
*
* solve_static(power): This functions computes the steady-state temperature
* profile of the chip.
*
* init_dynamic(power): This function is used in conjunction with
* step_dynamic() to perform dynamic thermal analysis. The init_dynamic()
* function computes the initial steady-state temperature, and must be called
* before step_dynamic() can be used. It stores the temperature profile as an
* internal state to allow subsequent calls to step_dynamic() to use the
* initial solution.
*
* step_dynamic(power, duration): This function performs dynamic thermal
* analysis for a simulation time of "duration". Either a time-domain solver,
* or a frequency-domain solver can be used. This can be specified from the
* program command-line arguments.
*
* zoom_and_solve_static(x_min, x_max, y_min, y_max, power): This function is
* the multiscale version of solve_static(). After using solve_static() and
* looking at the resulting temperature profile, it might be desired to zoom in
* a part of the chip by refining the element sizes to get more accurate
* temperature estimates.
*
* zoom_and_step_dynamic(x_min, x_max, y_min, y_max, power, duration): This
* function is the multiscale version of step_dynamic(). After using
* step_dynamic() and looking at the resulting temperature profile, it might
* be desired to zoom in a part of the chip by refining the element sizes as
* well as use a smaller time step size, to get more accurate temperature
* estimates. The zoom-in area is defined using x_min, x_max, y_min, and y_max.
* All the previous functions return a vector of Element_type containing the
* element locations, sizes, and temperature values. As an example, the
* solve_static function can be used as follows: */
vector<Element_type> thermal_profile;
thermal_profile = solve_static(power);
/* Step 4 */
/* Print out the temperature profile. A simple way to look at the temperatures
* would be to print them out directly. This can be done as follows: */
for(unsigned int i = 0; i < thermal_profile.size(); i++) {
cout << thermal_profile[i].center[X_] << " ";
cout << thermal_profile[i].center[Y_] << " ";
cout << thermal_profile[i].center[Z_] << " ";
cout << thermal_profile[i].temp << endl;
}
/* However, there is a function provided called print_hetero_eltvec_gnuplot(),
* which can be used to print out the active layer of the thermal_profile in a
* format that can be easily visualized using gnuplot. This function takes as
* input the thermal_profle and the required output grid size (for example
* 64x64). If the thermal profile was generated using one of the zooming
* functions (zoom_and_solve_static() or zoom_and_step_dynamic()), only the
* elements inside the specified box will be printed out */
print_hetero_eltvec_gnuplot(thermal_profile, 64);
/* Gnuplot can then be used to visualize the thermal profile generate. This can
* be simply done by writing the following commands in gnuplot:
* gnuplot> set pm3d map
* gnuplot> set palette rgbformulae 22,13,-31
* gnuplot> splot 'filename' */
/* Step 5 */
/* Find the temperature of certain devices on chip. This is done using the
* report_device_temperatures() function. This function takes as input the
* thermal profile returned from any of the functions in step 3, the layout
* file, and a box given by x_min, x_max, y_min, and y_max. This function
* computes the temperatures of all devices in the layout file (will be
* described later) that are inside the given box, based on the temperatures
* in the provided thermal profile, and the device BTE temperatures, if a
* look-up table file is provided. If a look-up table is not provided, the
* temperatures computed will be based on the provided thermal profile only.
* For more accurate device temperature results, the zoom_and_solve_static()
* function should be called multiple times before report_device_temperatures()
* is called. The zoom in area should be that containing the devices of
* interest. report_device_temperatures() returns a vector of Device_type,
* which contains information about the location of each device, its power
* consumption value and its temperature. The following shows the syntax for
* using the report_device_temperatures() function. */
vector<Device_type> devices;
string layout_file = "layout_filename";
devices = isac.report_device_temperatures(thermal_profile, layout_file, x_min, x_max, y_min, y_max);
/* Step 6 */
/* Print out the device temperatures. This can be done as follows: */
for(unsigned int i = 0; i < devices.size(); i++) {
cout << devices[i].loc[X_] << " " << devices[i].loc[Y_] << " ";
cout << devices[i].loc[Z_] << " " << devices[i].temp << endl;
}
/*===========================================================================*/
Chip File
The chip file contains the set of layers constituting the chip, as well as the
initial desired partitioning (grid) of each of the layers.
In each layer, the layer type is specified using one letter; 'p' for
power layer, 'm' for material layer, 'i' for interface layer. In the next line,
the layer dimensions are written; x_size y_size z_size. Power layers must have
a z_size of zero. In the following line, the thermal conductivity of the layer
material is specified, and in the line after that, the heat capacity is
specified. In the last line, the initial partitioning of the layer is
specified starting with the number of elements in the x-direction, followed by
the y-direction then the z-direction. The initial partitioning is only
specified for material and interface layers and not for power layers. This is
an example of a material layer (silicon) which is 10mmx10mmx100um, with thermal
conductivity of 142 W/m-K and heat capacity of 1.6e6 J/(m^3-K). The initial
partition is chosen to be 16x16x4.
m
10E-3 10E-3 100E-6
142
1.6E6
16 16 4
"EXAMPLE_CHIP_FILE" contains an example of a chip containing a silicon layer, a heat
spreader, and a heat sink.
If a non-homogeneous thermal conductivity/heat capacity for a layer is desired,
this can be done as follows:
m
10E-3 10E-3 100E-6
-1 condmap.txt
1.6E6
16 16 4
The "-1" signals the tool that a non-homogeneous thermal conductivity is
desired for this layer, and that the thermal conductivity map is specified in a
file called "condmap.txt". Here's an example of a conductivity map file:
142.3
0.0 0.0 1E-6 2E-6 50.0
1E-3 -2E-3 3E-6 4E-6 70.0
-3E-3 -4E-3 5E-6 6E-6 90.0
The first value in the file is the bulk conductivity of the layer. The three
other lines specify three areas that have a conductivity different than the
bulk. An area is specified by its x and y coordinates and sizes. The x and y
coordinates lie in the center of the area. So for example, the third line in
the file specifies an area that is centered at (1E-3, -2E-3) and has a size of
3umx4um. The conductivity in this area is 70.0 W/m-K. A non-homogeneous heat
capacity for a layer can be specifies in a similar way.
/*===========================================================================*/
Floorplan File
The floorplan file contains the different power blocks in the active layer.
Each line corresponds to a block, which is specified by x_min, x_max, y_min and
y_max. For example a block that goes from x = -5mm to x = -4mm and from y = 1mm
to y = 2mm can be specified as follows:
-5E-3 -4E-3 1E-3 2E-3
See "EXAMPLE_FLOORPLAN_FILE" for an example of a floorplan of 64x64 uniform blocks.
/*===========================================================================*/
Power File
The power file contains the power values corresponding to each block in the
floorplan file. Assume we have several power profiles at timepoints T1 ms, T2 ms,
..., Tn ms. The simulation ending time is Te ms. The power file format is detailed as follows:
Power_profile_at_0ms
T1 ms
Power_profile_at_T1_ms
T2 ms
Power_profile_at_T2_ms
T3 ms
...
Tn ms
Power_profile_at_Tn_ms
Te ms
For each block in the floorplan, the associated power values at time 0 are
provided, one value per line. Following the power profile are the remaining
timepoints along with the corresponding power profiles. The allowable time
units are "s", "ms", "us", "ns", and "ps". Finally, the simulation ending time
is supplied at the end of the file. Note that it is required that T1 < T2 < T3
< ... < Tn < Te. The total number of power profiles should be at least 1. More
details can be found in "EXAMPLE_POWER_FILE".
/*===========================================================================*/
Layout File
The layout file contains the device locations and their power consumption
values. It is not necessary to specify the locations of all devices on-chip.
Only the devices whose temperatures are to be computed can be specified. A
device can be specified using the following syntax:
<x_coordinate> <y_coordinate> <z_coordinate> <power consumption in Watts>
The z-coordinate is that corresponding to the power layer in which the device
lies.
A small example layout file is in "EXAMPLE_LAYOUT_FILE".
/*===========================================================================*/
Device input file
The device input file is used to describe all details of the device, including
its geometry, materials, and solver options. The semantics of this file are as
follows:
<Global Parameters>
<Material Definition>
<Substrate Definition>
<Device Definition>
Each of the those components will be described next.
Global Parameters:
------------------
iter : The iteration parameter (default = 10)
When the hybrid Fourier/BTE solver is used, the iteration parameter controls
how many iterations are executed for the Fourier/BTE region, before the other
solver is called. For example, for iter = 4, the Fourier solver will be
executed for 4 iterations, the boundary conditions will be updated, then the BTE
solver will be executed for 4 iterations, and so on. Depending on the device
being solved, this number might affect the overall convergence time.
expand_factor: The BTE region expansion factor (default = 10)
The number of phonon mean free paths (mfp), by which the BTE region will be
expanded in each direction. For example, if the mfp = 40nm, and expand_factor =
2, the BTE region will be expanded by 80nm in each direction (80nm in +ve x,
80nm in -ve x, 80nm in +ve y, 80nm in -ve y, 80nm in +ve z, 80nm in -ve z).
Since the BTE solver is significantly slower than the Fourier one, increasing
this number will result in a longer execution time, however results will have
better accuracy.
k_stab: The attenuation factor for maintaining stability in the hybrid
Fourier/BTE solver (default = 1)
In the hybrid Fourier/BTE solver, the boundary conditions are continuously
updated after each solver is done with a number of iterations. In some cases
such as SOI or FinFET devices, this process leads to divergence of results. If
this is the case, the divergence problem can be overcome by setting k_stab to a
value lower than 1 (a smaller value leads to slower boundary updates and a more
stable solving process).
t_ini: The initial temperature for all device elements (in Kelvin)
All elements will be initialized to this value before the solving process
starts.
all_bte: When set to 1, this flag signals the program to apply the BTE solver
for all the elements. Setting all_bte to 1 is done using the following syntax:
all_bte 1
all_fourier: When set to 1, this flag signals the program to apply the Fourier
solver for all the elements. Setting all_fourier to 1 is done using the
following syntax:
all_fourier 1
If neither of the previous flags are set, the hybrid Fourier/BTE solver is
used.
transient: The transient simulation flag
When set to 1, transient (dynamic) analysis will be carried out for the device.
The simulation time, and the simulation step must be specified. The syntax is
as follows:
transient <simulation step> <simulation time>
cells_x, cells_y, cells_z: The number of cells by which the device will be
partitioned in each direction.
Material Definition:
--------------------
A material is defined by the phonon group velocity, the phonon relaxation time,
the volumetric specific heat, and the thermal conductivity. The reference
temperature for the volumetric specific heat should also be specified. The
syntax for defining the material is as follows:
% material <Material name>
vg <Group velocity value>
t_rel <Relaxation time value>
cv <Volumetric specific heat value>
k_cond <Thermal conductivity value>
temp <Reference temperature for the volumetric specific heat in Kelvin>
%
As many materials as needed can be defined this way.
Substrate Definition:
---------------------
The device substrate is defined by its material, its x, y, and z coordinates
(starting points), its dimensions and its boundary conditions.
The boundary condition for each of the 6 surfaces can be specified
independently. There are two surfaces perpendicular to the x-axis which we call
the west and east surfaces, two surfaces perpendicular to the y-axis which we
call the south and north surfaces, and two surfaces perpendicular to the
z-axis which we call the bottom and top surfaces. The west surface is referred
to by "x 0", while the east one is referred to by "x 1". Similarly the south
surface is referred to by "y 0", and the north surface is referred to by
"y 1", and so on.
The types of boundary conditions supported in this program are constant
temperature, insulating, specular, and diffusive boundaries.
Constant temperature boundaries can be specified as follows:
t_bound <x or y or z> <0 or 1> <temperature value in Kelvin>
For example:
t_bound x 0 300
sets the west surface to be a constant temperature boundary of 300 Kelvin.
Insulating, specular, and diffusive boundary conditions can be specified as:
<ins or spec or diff> <x or y or z> <0 or 1>
For example:
diff y 1
sets the north surface to be diffusive.
The syntax for defining the substrate is as follows:
% substrate
material <Material Name>
coordinates <x> <y> <z>
lengthx <its length in the x-direction>
lengthy <its length in the y-direction>
lengthz <its length in the z-direction>
<Boundary conditions for the 6 surfaces>
%
Note that the material name must be defined in the material definition part of
the file.
Device Definition:
------------------
A device consists of one or more pieces. The implementation is done this way to
allow describing complex device structures such as FinFETs. The device can be
defined using the following syntax:
% device
<Global parameters for the device>
%
<Piece 1>
%
<Piece 2>
% end device
The global parameters for the device are the amount of control angles per
octant, the transivity factors from the 6 device surfaces, and the heat sources
inside the device. The amount of control angles per octant are
specified using the azimuthal angle discretization (nphi) and the elevation
angle discretization (ntheta), i.e. the following:
nphi 2
ntheta 2
would result in a total of 32 control angles (2x2 = 4 per octant x 8 octants =
32).
The transivity factors define the amount of heat transivity from the
device boundaries, which depends on the materials on the two sides. A value of
1 indicates a fully transmittive boundary (for example in the case the
materials on the two sides are the same), and a value of 0 indicates a fully
reflective boundary. The transivity factor for each of the surfaces can be
specified independently as follows:
trans_factor <x or y or z> <0 or 1> <transivity factor value>
For example:
trans_factor z 0 0.7
indicates that the bottom surface of the device is 70% transmittive.
The heat source simulates the device heating due to the collision of electrons
traveling through the channel with the drain. The heat source is defined by its
value in Watts, and its coordinates. It is usually defined to be the size of
the device channel. The syntax for a heat source definition is as follows:
source <value in Watts> <x_min> <x_max> <y_min> <y_max> <z_min> <z_max>
For example:
source 1e-5 100e-9 200e-9 50e-9 150e-9 90e-9 100e-9
defines a heat source with a value of 10 uWatts, its west surface is at x =
100nm, its east surface is at x = 200nm, its south surface is at y = 50nm, its
north surface is at y = 150nm, its bottom surface is at z = 90nm, and its top
surface is at 100nm. i.e., the source is 100nm x 100nm x 10nm. The x, y, and z
coordinates are relative to the substrate coordinates defined in the substrate
part.
A transient heat source (for transient simulations) is specified using the
"trans_source" keyword. The current transient waveform supported is a pulse
defined by its width (on time), and the pulse offset from time t = 0.
The parameters for the transient source are the same as
those for the normal source, with 2 extra parameters that define the pulse
offset and on time. The syntax for specifying it the transient source is as
follows:
source <value in Watts> <x_min> <x_max> <y_min> <y_max> <z_min> <z_max> <offset
time> <on time>
Next, the pieces of the device are defined. Each piece is defined by its
material, its x, y, z coordinates and lengths. The syntax is as follows:
material <Material name>
coordinates <x-coodinate> <y-coodinate> <z-coodinate>
lengthx <value>
lengthy <value>
lengthz <value>
Finally, a '#' at the beginning of a line indicates that this line is a
comment.
An example device file is provided in "EXAMPLE_DEVICE_FILE".
/*===========================================================================*/
Command Line Arguments
For convenience purposes, command line arguments can be supplied to
ISAC2. The most common options are:
-d <file> : for specifying the device file
-c <file> : for specifying the chip file
-f <file> : for specifying the floorplan file
-p <file> : for specifying the power file
-y <file> : for specifying the layout file
-l <file> : for specifying the look-up table file
-s <option> : for specifying the solver type (use 't' for the time-domain
solver and 'f' for the frequency-domain solver)
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ISAC2.tar (1.4 MB)
