Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library.

One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed.

Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog .

It has Tcl/Python API support.

ipxact2verilog - Generate Verilog module from IP-XACT definition

ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component definition

verilog2ipxact - Generates IP-XACT definition from Verilog modules

vhdl2ipxact - Generates IP-XACT definition from VHDL source

ipxactcoherencycheckerverilog / ipxactcoherencycheckervhdl - Validates IP-XACT Component definition with RTL

validateipxact - IP-XACT Linting tool

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Additional Project Details

Operating Systems

Linux, Windows

User Interface

Java SWT

Programming Language

Python, Tcl, Java

Related Categories

Python Electronic Design Automation (EDA) Software, Tcl Electronic Design Automation (EDA) Software, Java Electronic Design Automation (EDA) Software

Registered

2024-01-20