Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.

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License

BSD License

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Additional Project Details

Intended Audience

Information Technology, Science/Research, Developers

User Interface

Command-line

Programming Language

C++, VHDL/Verilog

Related Categories

C++ Code Generators, C++ Compilers, C++ Electronic Design Automation (EDA) Software, VHDL/Verilog Code Generators, VHDL/Verilog Compilers, VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2006-10-16