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Open-source interpreted Verilog simulator with a feature set and performance similar to Verilog-XL. Implements all IEEE 1364-1995 features along with some Verilog-2001 features. Full support for Verilog PLIs.

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Categories

Simulation, Electronic Design Automation (EDA)

License

GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Operating Systems

Linux, Mac

Intended Audience

End Users/Desktop, Engineering

User Interface

Console/Terminal

Registered

2009-04-24
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