Open-source interpreted Verilog simulator with a feature set and performance similar to Verilog-XL. Implements all IEEE 1364-1995 features along with some Verilog-2001 features. Full support for Verilog PLIs.
License
GNU General Public License version 2.0 (GPLv2)
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User Ratings
ease
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0 / 5
features
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0 / 5
design
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support
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Additional Project Details
Intended Audience
End Users/Desktop, Engineering
User Interface
Console/Terminal