High Accuracy Approx Adder for FPGAs Files

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COMPUTER SCIENCES GROUP - DEPARTMENT OF AVIONICS ENGG - COLLEGE OF AERONAUTICAL ENGINEERING
          NATIONAL UNIVERSITY OF SCIENCES AND TECHNOLOGY, ISLAMABAD, PAKISTAN
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  This code is provided here for educational purpose(s) only.  Kindly contact the author on 
  nomani@cae.nust.edu.pk for queries / questions. This code is the intellectual property of
  the author(s) and requires permission(s) for use. View bottom disclaimer for further info. 
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Verilog_Models

These are Verilog codes for DCT and used Approximate Adder Models. Copy paste or import the 
v files in Xilinx_ISE_14.7 project and run Synthesis with Balanced settings to get results.

Matlab_Models

These are interconnected m files. To use to specific approx_adder, just call it as a function
in Fcn_DCTCompress file and replace an actual addition. If you wish to obtain accurate adder
results, just comment out the part where Approx_adder_Fcn is being called. 

For any questions, querries or details see my following publication(s) through google scholar:

Tuaha Nomani, Mujahid Mohsin, and Faizana Naeem, "A Novel Approximate Adder Design Methodology
with Single LUT Delay for Fault-tolerant FPGA-based Systems", in Intellect 2019.

Tuaha Nomani, Mujahid Mohsin, and Zahid Pervaiz, "H3AL-FPGA : High Accuracy Approximate Adder
for HD Image Optimization Applications", Electronics 8, no. 1 (2019): 51.


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Disclaimer  :  Any disclosure, copying, or distribution of this code, or the taking of any 
action based on it, is strictly prohibited and may be unlawful. The University specifically
denies any responsibility for the accuracy or quality of information obtained with herein. 
Any view(s) and opinion(s) expressed are only those of the author(s) and do not necessarily 
represent those of the University and the University accepts no liability, whatsoever, for 
any losses/damages incurred/caused to any party as a result of the use of such information.
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