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S16E22.zip (1.4 kB)
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| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| Verilog_Exemplo11_PortabilidadeQuartus.zip | 2017-10-02 | 1.5 MB | |
| Verilog_Exemplo10_DHT11.zip | 2017-10-02 | 3.0 MB | |
| Verilog_Exemplo9_START.zip | 2017-09-03 | 3.2 MB | |
| Verilog_Exemplo6_StateMachine.zip | 2017-09-03 | 1.7 MB | |
| Verilog_Exemplo8_7Seg.zip | 2017-09-03 | 2.7 MB | |
| Verilog_Exemplo7_SPI_Out.zip | 2017-09-03 | 1.7 MB | |
| Verilog_Exemplo5_TRISTATE.zip | 2017-07-09 | 2.9 MB | |
| Verilog_Exemplo4_ClockDiv.zip | 2017-07-09 | 1.6 MB | |
| Verilog_Exemplo3_PLL.zip | 2017-06-09 | 693.9 kB | |
| Verilog_Exemplo2_MUX.zip | 2017-06-03 | 681.2 kB | |
| Verilog_Exemplo1.zip | 2017-05-15 | 951.6 kB | |
| Avt_S6LX9_MicroBoard_UCF_110804.ucf | 2017-05-15 | 15.2 kB | |
| Totals: 12 Items | 20.6 MB | 2 | |