ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides.

It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.

Features

  • Compile to complete vendor-specific project from largely vendor-neutral source
  • Automated timing-requirement generation
  • Proceedural state-machine programming model
  • Bit- and timing-accurate circuit description
  • Compile-time scripting

Project Samples

Concept Block Diagram

Project Activity

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Categories

Code Generators, Compilers, Programming Languages

License

GNU General Public License version 3.0 (GPLv3)

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Additional Project Details

Languages

English

Intended Audience

Developers, Engineering, Science/Research

User Interface

Command-line

Programming Language

C++

Related Categories

C++ Code Generators, C++ Compilers, C++ Programming Languages

Registered

2015-10-26
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