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From: <jgr...@us...> - 2003-03-26 00:29:42
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv4172/include/asm-xtensa
Modified Files:
hardirq.h
Log Message:
Add release_irqlock definition.
Index: hardirq.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/hardirq.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** hardirq.h 15 Feb 2003 02:02:40 -0000 1.2
--- hardirq.h 26 Mar 2003 00:29:38 -0000 1.3
***************
*** 43,50 ****
#define hardirq_endlock(cpu) do { } while (0)
! #define irq_enter(cpu, irq) (local_irq_count(cpu)++)
#define irq_exit(cpu, irq) (local_irq_count(cpu)--)
#define synchronize_irq() barrier();
#else
--- 43,52 ----
#define hardirq_endlock(cpu) do { } while (0)
! #define irq_enter(cpu, irq) (local_irq_count(cpu)++)
#define irq_exit(cpu, irq) (local_irq_count(cpu)--)
#define synchronize_irq() barrier();
+
+ #define release_irqlock(cpu) do { } while (0)
#else
|
|
From: <joe...@us...> - 2003-03-21 18:53:40
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv5812/include/asm-xtensa Modified Files: sysxtensa.h Log Message: Add kernel support for additional atomic operations that user tasks cannot perform themselves. glibc will use them. Index: sysxtensa.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/sysxtensa.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** sysxtensa.h 28 Aug 2002 16:11:31 -0000 1.1.1.1 --- sysxtensa.h 21 Mar 2003 18:11:54 -0000 1.2 *************** *** 17,23 **** #define XTENSA_RESERVED 0 /* don't use this */ #define XTENSA_ATOMIC_SET 1 /* atomically set variable */ /* Keep this count last. */ ! #define XTENSA_SYSXTENSA_COUNT 2 /* count of sysxtensa functions */ --- 17,26 ---- #define XTENSA_RESERVED 0 /* don't use this */ #define XTENSA_ATOMIC_SET 1 /* atomically set variable */ + #define XTENSA_ATOMIC_EXG_ADD 2 /* atomically exchange memory and add */ + #define XTENSA_ATOMIC_ADD 3 /* atomically add to memory */ + #define XTENSA_ATOMIC_CMP_SWP 4 /* atomically compare and swap */ /* Keep this count last. */ ! #define XTENSA_SYSXTENSA_COUNT 5 /* count of sysxtensa functions */ |
|
From: <joe...@us...> - 2003-03-21 18:53:39
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv5812/arch/xtensa/kernel
Modified Files:
sys.S sysxtensa.c
Log Message:
Add kernel support for additional atomic operations that user tasks cannot perform themselves. glibc will use them.
Index: sys.S
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/sys.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** sys.S 13 Feb 2003 00:17:21 -0000 1.3
--- sys.S 21 Mar 2003 18:11:53 -0000 1.4
***************
*** 98,102 ****
/* Same as handle_sys_kernel, except user-mode version. The
* distinct kernel and user versions avoid the overhead of
! * testing PS.PSTK bit to determine whether to branch to
* handle_kernel or handle_user. */
--- 98,102 ----
/* Same as handle_sys_kernel, except user-mode version. The
* distinct kernel and user versions avoid the overhead of
! * testing PS.UM bit to determine whether to branch to
* handle_kernel or handle_user. */
***************
*** 207,210 ****
--- 207,212 ----
+ /* XTFIXME: The last three unhandled cases present an optimization opportunity. */
+
.data
.align 4
***************
*** 212,217 ****
.word quick_unhandled
.word quick_atomic_set
! #if XTENSA_SYSXTENSA_COUNT != 2
#error Number of sysxtensa calls and registered handlers are different
#endif
--- 214,222 ----
.word quick_unhandled
.word quick_atomic_set
+ .word quick_unhandled
+ .word quick_unhandled
+ .word quick_unhandled
! #if XTENSA_SYSXTENSA_COUNT != 5
#error Number of sysxtensa calls and registered handlers are different
#endif
***************
*** 867,876 ****
/* Make PS suitable for windowed-register calls in kernel:
* INTLEVEL = 0 // clear for panic() and printk()
! * EXCM = 0 // leave exception mode
! * PSTK (UM) = 0 // enter kernel mode
! * RING = 0 // assume kernel memory
! * OWB = 0 // don't care
! * CALLINC = 0 // don't care
! * WOE = 1 // required for "entry" insn
*/
movi a7, XCHAL_PS_WOE_MASK
--- 872,881 ----
/* Make PS suitable for windowed-register calls in kernel:
* INTLEVEL = 0 // clear for panic() and printk()
! * EXCM = 0 // leave exception mode
! * UM = 0 // enter kernel mode
! * RING = 0 // assume kernel memory
! * OWB = 0 // don't care
! * CALLINC = 0 // don't care
! * WOE = 1 // required for "entry" insn
*/
movi a7, XCHAL_PS_WOE_MASK
Index: sysxtensa.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/sysxtensa.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** sysxtensa.c 28 Feb 2003 01:53:09 -0000 1.2
--- sysxtensa.c 21 Mar 2003 18:11:53 -0000 1.3
***************
*** 31,37 ****
switch(cmd) {
! case XTENSA_ATOMIC_SET: {
/* Sets value atomically and returns original value. */
p = (int *) arg1;
--- 31,39 ----
switch(cmd) {
! case XTENSA_ATOMIC_SET:
! {
/* Sets value atomically and returns original value. */
+ /* int sysxtensa (XTENSA_ATOMIC_SET, ptr, val, unused); */
p = (int *) arg1;
***************
*** 59,62 ****
--- 61,141 ----
: "=a" (tmp), "=a" (retval)
: "a" (p), "a" (arg2), "i" (-EFAULT)
+ : "a15"
+ );
+ goto out;
+ }
+
+ case XTENSA_ATOMIC_EXG_ADD:
+ case XTENSA_ATOMIC_ADD:
+ {
+
+ /* Atomically add value to memory, return original value. */
+
+ /* int sysxtensa (XTENSA_ATOMIC_EXG_ADD, ptr, val, unused); */
+ /* int sysxtensa (XTENSA_ATOMIC_ADD, ptr, val, unused); */
+
+ p = (int *) arg1;
+ retval = verify_area(VERIFY_WRITE, p, sizeof(*p));
+ if (retval)
+ return retval;
+
+ __asm__ __volatile__(
+ " rsil a15, "XTSTR(LOCKLEVEL)"\n"
+ "1: l32i %1, %2, 0 \n"
+ " add %3, %3, %1 \n"
+ "2: s32i %3, %2, 0 \n"
+ "5: wsr a15, "XTSTR(PS)" \n"
+ " rsync \n"
+ " .section .fixup,\"ax\" \n"
+ " .align 4 \n"
+ "6: .word 5b \n"
+ "7: l32r %0, 6b \n"
+ " movi %1, %4 \n"
+ " jx %0 \n"
+ " .previous \n"
+ " .section __ex_table,\"a\" \n"
+ " .word 1b, 7b \n"
+ " .word 2b, 7b \n"
+ " .previous \n"
+ : "=a" (tmp), "=a" (retval)
+ : "a" (p), "a" (arg2), "i" (-EFAULT)
+ : "a15"
+ );
+ goto out;
+ }
+
+ case XTENSA_ATOMIC_CMP_SWP:
+ {
+ /* Atomically store newval iif *ptr == oldval */
+ /* int sysxtensa (XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval); */
+
+ p = (int *) arg1;
+ retval = verify_area(VERIFY_WRITE, p, sizeof(*p));
+ if (retval)
+ return retval;
+
+ __asm__ __volatile__(
+ " rsil a15, "XTSTR(LOCKLEVEL)"\n"
+ "1: l32i %1, %2, 0 \n"
+ " beq %1, %3, 2f \n"
+ " movi %1, 0 \n"
+ " j 5f \n"
+ "2: s32i %4, %2, 0 \n"
+ " movi %1, 1 \n"
+ "5: wsr a15, "XTSTR(PS)" \n"
+ " rsync \n"
+ " .section .fixup,\"ax\" \n"
+ " .align 4 \n"
+ "6: .word 5b \n"
+ "7: l32r %0, 6b \n"
+ " movi %1, %5 \n"
+ " jx %0 \n"
+ " .previous \n"
+ " .section __ex_table,\"a\" \n"
+ " .word 1b, 7b \n"
+ " .word 2b, 7b \n"
+ " .previous \n"
+ : "=a" (tmp), "=a" (retval)
+ : "a" (p), "a" (arg2), "a" (arg3), "i" (-EFAULT)
: "a15"
);
|
|
From: <ma...@us...> - 2003-03-20 20:49:13
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv4191
Modified Files:
traps.c
Log Message:
Make illegal instruction traps visible to the OCD debugger if present;
and use the new fake-debug-EXCCAUSE macro rather than hardcode its value.
Index: traps.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/traps.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** traps.c 13 Feb 2003 19:35:05 -0000 1.10
--- traps.c 20 Mar 2003 20:49:08 -0000 1.11
***************
*** 361,364 ****
--- 361,366 ----
}
#endif
+ /*XTFIXME: Use signals other than SIGTRAP for certain
+ * debug causes reported in regs->reserved1 ?: */
force_sig(SIGTRAP, current);
} else {
***************
*** 506,511 ****
set_c_except_handler (XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION,
handle_illegal_instruction);
! set_c_except_handler (31, do_debug);
atomic_inc(&init_mm.mm_count); /* XXX UP? */
--- 508,515 ----
set_c_except_handler (XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION,
handle_illegal_instruction);
+ /*XTFIXME: for internal debug:*/
+ set_except_vector(EXC_CODE_USER + XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, handle_user_debug);
! set_c_except_handler (FAKE_EXCCAUSE_DEBUG, do_debug);
atomic_inc(&init_mm.mm_count); /* XXX UP? */
|
|
From: <ma...@us...> - 2003-03-20 20:47:43
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv2825 Modified Files: pci-dma.c Log Message: Use a safer cache invalidation call (_writeback_inv) for PCI DMA. Using _invalidate can throw away dirty cache data, so much more investigation is needed to guarantee it is safe to use here. Index: pci-dma.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/pci-dma.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** pci-dma.c 17 Jan 2003 00:31:30 -0000 1.2 --- pci-dma.c 20 Mar 2003 20:47:35 -0000 1.3 *************** *** 52,56 **** BUG(); case PCI_DMA_FROMDEVICE: /* invalidate only */ ! xthal_dcache_region_invalidate(vaddr, size); break; case PCI_DMA_TODEVICE: /* writeback only */ --- 52,60 ---- BUG(); case PCI_DMA_FROMDEVICE: /* invalidate only */ ! /* perhaps not 100% safe? -- XTFIXME */ ! /*xthal_dcache_region_invalidate(vaddr, size);*/ ! ! /* this is always safe: */ ! xthal_dcache_region_writeback_inv(vaddr, size); break; case PCI_DMA_TODEVICE: /* writeback only */ |
|
From: <ma...@us...> - 2003-03-20 20:45:43
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv1534 Modified Files: handlers.S Log Message: Fix debug exception handler to at least reasonably handle the case where PS.EXCM was set when the debug exception occurred. For now, just try to ignore such exceptions; later, perhaps we can make kgdb handle them if it is active. Index: handlers.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v retrieving revision 1.14 retrieving revision 1.15 diff -C2 -d -r1.14 -r1.15 *** handlers.S 13 Feb 2003 18:19:20 -0000 1.14 --- handlers.S 20 Mar 2003 20:45:37 -0000 1.15 *************** *** 76,79 **** --- 76,80 ---- #include <asm/offset.h> #include <asm/pgtable.h> + #include <asm/processor.h> #define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART register in bits */ *************** *** 1024,1028 **** * saved in pt_regs, but we do anyway because it makes the algorithm * simpler. ! * The algoritm is to first save all panes lower than the active one, * and then save all the panes above the active one. We can only touch * a2 and a3. */ --- 1025,1029 ---- * saved in pt_regs, but we do anyway because it makes the algorithm * simpler. ! * The algorithm is to first save all panes lower than the active one, * and then save all the panes above the active one. We can only touch * a2 and a3. */ *************** *** 2819,2831 **** ! /* Debug Exception Handler * ! * On entry, a0 is preserved in EXCSAVE[DEBUGLEVEL]. * * This handler will set things up to look like either a kernel or user ! * exception occurred, depending if the debug trap happened in kernel or user ! * code, respectively, and then jump to the common exception handling code. ! * Thus, rfi is never called for debug interrupts. Instead, an the rfe in ! * the common exception path is called. * */ --- 2820,2842 ---- ! /* ! * Debug Exception Handler ! * ! * This handler assumes the following vector implementation: ! * ! * xsr a0, EXCSAVE + XCHAL_DEBUGLEVEL ! * jx a0 * ! * Thus on entry here, a0 has been saved in EXCSAVE_[DEBUGLEVEL]. * * This handler will set things up to look like either a kernel or user ! * exception occurred, depending on whether the debug exception happened ! * in kernel or user code, respectively, and then jump to the common ! * exception handling code. ! * Thus, rfi is usually never called for debug exceptions. Instead, ! * an rfe in the common exception path is called. ! * However, if PS.EXCM was set when the debug exception occurred, ! * it is handled differently; the exception is simply "ignored" ! * as much as possible (XTFIXME: pass such occurrences to kgdb if active). * */ *************** *** 2834,2842 **** handle_debug: - wsr a2, DEPC // preserve a2 so we can use it rsr a0, PS // Check if in user or kernel mode ! extui a0, a0, PS_UM_SHIFT, 1 ! bnez a0, 1f // jump if in user mode ! addi a0, a1, -(16+PT_SIZE) // use system stack s32i a1, a0, PT_AREG1 // save previous sp --- 2845,2854 ---- handle_debug: rsr a0, PS // Check if in user or kernel mode ! wsr a2, DEPC // preserve a2 so we can use it ! bbsi.l a0, PS_EXCM_SHIFT, 3f // jump if in exception mode ! bbsi.l a0, PS_UM_SHIFT, 1f // jump if in user mode ! ! // Kernel mode: addi a0, a1, -(16+PT_SIZE) // use system stack s32i a1, a0, PT_AREG1 // save previous sp *************** *** 2844,2873 **** movi a2, EXCTYPE_KERNEL // mark as a kernel exception j 2f - 1: - /* Switch to system stack. Variable kernelsp is a pointer to - * the system stack already decremented by 16+PT_SIZE. */ ! movi a0, kernelsp l32i a0, a0, 0 // load system stack value from variable s32i a1, a0, PT_AREG1 // save task's sp mov a1, a0 // set sp to system stack ! movi a2, EXCTYPE_USER // mark as a kernel exception ! 2: ! movi a0, 0 // Initialize ICOUNT and ICOUNTLEVEL wsr a0, ICOUNTLEVEL // so we don't get any ICOUNT wsr a0, ICOUNT // exceptions in the kernel. isync ! movi a0, 31 // set up "dummy" debug exception cause wsr a0, EXCCAUSE rsr a0, EPC + XCHAL_DEBUGLEVEL // Put PC into EPC1 for the wsr a0, EPC_1 // generic exception code. - rsr a0, EPS + XCHAL_DEBUGLEVEL // Put PS wth EXCM on into PS #if 1 ! s32i a0, a1, PT_RESERVED0 #endif - addi a0, a0, XCHAL_PS_EXCM_MASK // for the generic exception wsr a0, PS // code. --- 2856,2890 ---- movi a2, EXCTYPE_KERNEL // mark as a kernel exception j 2f ! // User mode: ! // Switch to system stack. Variable kernelsp is a pointer to ! // the system stack already decremented by 16+PT_SIZE. ! 1: movi a0, kernelsp ! //slot l32i a0, a0, 0 // load system stack value from variable + movi a2, EXCTYPE_USER // mark as a kernel exception s32i a1, a0, PT_AREG1 // save task's sp mov a1, a0 // set sp to system stack ! ! 2: movi a0, 0 // Initialize ICOUNT and ICOUNTLEVEL wsr a0, ICOUNTLEVEL // so we don't get any ICOUNT wsr a0, ICOUNT // exceptions in the kernel. isync ! movi a0, FAKE_EXCCAUSE_DEBUG // set up "dummy" debug exception cause wsr a0, EXCCAUSE + #if 1 + rsr a0, DEBUGCAUSE // save DEBUGCAUSE while it is live + s32i a0, a1, PT_RESERVED1 + #endif + rsr a0, EPC + XCHAL_DEBUGLEVEL // Put PC into EPC1 for the wsr a0, EPC_1 // generic exception code. + rsr a0, EPS + XCHAL_DEBUGLEVEL // Put PS wth EXCM on into PS #if 1 ! s32i a0, a1, PT_RESERVED0 // save EPS while it is live #endif addi a0, a0, XCHAL_PS_EXCM_MASK // for the generic exception wsr a0, PS // code. *************** *** 2882,2885 **** --- 2899,2984 ---- j _excCommonException // jump to common exception code + + // Exception mode: + // + // Here, a debug exception wasn't expected. + // (Simulating a general exception would mean simulating + // a double exception, and isn't what we want.) + // Possible reasons for getting here include unhandled + // exceptions (that cause execution of a BREAK instruction), + // and kernel bugs in critical exception assembly code. + // + // Assume there is no debugger present + // (XTFIXME: pass this exception to kgdb) + // and minimally handle the exception. + // In other words, skip over BREAK instructions, + // let ICOUNT continue counting, etc). + // The end result of executing this default handler + // is almost as if no debug exception had occurred, + // eg. as if PS.INTLEVEL >= DEBUGLEVEL (with some + // exceptions, such as disabling of IBREAK and + // DBREAK when encountered). + // + // If multiple debug causes are present, only handle one. + // (Any remaining ones will normally trigger after RFI.) + // + 3: + rsr a0, DEBUGCAUSE // get cause of debug exception + + bbci.l a0, DEBUGCAUSE_ICOUNT_SHIFT, 1f // ICOUNT trap? + movi a0, 0 + wsr a0, ICOUNT // clear ICOUNT + j 3f + + /* + * Ensure that we have IBREAKs, otherwise the IBREAKENABLE + * special register is not there: + */ + #if XCHAL_NUM_IBREAK > 0 + 1: bbci.l a0, DEBUGCAUSE_IBREAK_SHIFT, 1f // IBREAK match? + movi a0, 0 + wsr a0, IBREAKENABLE // disable IBREAK traps + j 3f + #endif + + /* Also check for DBREAK registers: */ + #if XCHAL_NUM_DBREAK > 0 + 1: bbci.l a0, DEBUGCAUSE_DBREAK_SHIFT, 1f // DBREAK match? + movi a0, 0 + wsr a0, DBREAKC_0 // disable DBREAK register 0 + # if XCHAL_NUM_DBREAK > 1 + wsr a0, DBREAKC_1 // disable DBREAK register 1 + # endif + j 3f + #endif + + 1: bbci.l a0, DEBUGCAUSE_BREAK_SHIFT, 1f // BREAK instruction? + //rsr a0, EPC+XCHAL_DEBUGLEVEL // get PC pointing to BREAK + //l8ui a0, a0, 1 // get first 4-bit operand of BREAK (in 2nd byte) + //extui a0, a0, (XCHAL_HAVE_BE*4), 4 // pos depends on endianness + //bnei a0, 1, 3f // is it a BREAK 1,x instruction? + rsr a0, EPC+XCHAL_DEBUGLEVEL // get PC pointing to BREAK + addi a0, a0, 3 // skip BREAK instruction + wsr a0, EPC+XCHAL_DEBUGLEVEL // update PC + j 3f + + 1: bbci.l a0, DEBUGCAUSE_BREAKN_SHIFT, 1f // BREAK.N instruction? + rsr a0, EPC+XCHAL_DEBUGLEVEL // get PC pointing to BREAK.N + addi a0, a0, 2 // skip BREAK.N instruction + wsr a0, EPC+XCHAL_DEBUGLEVEL // update PC + j 3f + + 1: bbci.l a0, DEBUGCAUSE_DEBUGINT_SHIFT, 1f // debug interrupt? + // Nothing to do... + j 3f + + 1: // Unknown debug case? ignore + + 3: movi a0, handle_debug // re-setup handler address + xsr a0, EXCSAVE+XCHAL_DEBUGLEVEL // restore a0 + rfi XCHAL_DEBUGLEVEL // return from debug exception + + + |
|
From: <ma...@us...> - 2003-03-20 20:42:41
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv32508 Modified Files: processor.h Log Message: Add explicit constant for debug-specific fake EXCCAUSE value allocation. Index: processor.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/processor.h,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** processor.h 13 Feb 2003 22:25:20 -0000 1.5 --- processor.h 20 Mar 2003 20:42:37 -0000 1.6 *************** *** 28,31 **** --- 28,44 ---- + /* + * General exception cause assigned to debug exceptions. + * Debug exceptions go to their own vector, rather than + * the general exception vectors (user, kernel, double); + * and their specific causes are reported via DEBUGCAUSE + * rather than EXCCAUSE. However it is sometimes convenient + * to redirect debug exceptions to the general exception + * mechanism. To do this, an otherwise unused EXCCAUSE + * value was assigned to debug exceptions for this purpose: + */ + #define FAKE_EXCCAUSE_DEBUG 31 + + #ifndef __ASSEMBLY__ |
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From: <ma...@us...> - 2003-03-20 20:41:18
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv31436
Modified Files:
signal.c
Log Message:
Fix incorrect stack alignment in Xtensa-specific signal handling.
Index: signal.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/signal.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** signal.c 7 Feb 2003 02:03:35 -0000 1.3
--- signal.c 20 Mar 2003 20:41:09 -0000 1.4
***************
*** 403,407 ****
sp = current->sas_ss_sp + current->sas_ss_size;
! return (void *)((sp - frame_size) & -8ul);
}
--- 403,407 ----
sp = current->sas_ss_sp + current->sas_ss_size;
! return (void *)((sp - frame_size) & -16ul);
}
***************
*** 603,607 ****
#if DEBUG_SIG
! printk("SIG deliver (%s:%d): signal=%d sp=%p pc=%08x\n",
current->comm, current->pid, signal, frame, regs->pc);
#endif
--- 603,607 ----
#if DEBUG_SIG
! printk("SIG rt deliver (%s:%d): signal=%d sp=%p pc=%08x\n",
current->comm, current->pid, signal, frame, regs->pc);
#endif
|
|
From: <jgr...@us...> - 2003-03-12 00:36:35
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv25808
Modified Files:
div64.h
Log Message:
Correct 64-bit division.
Index: div64.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/div64.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** div64.h 15 Feb 2003 02:02:40 -0000 1.2
--- div64.h 12 Mar 2003 00:36:31 -0000 1.3
***************
*** 13,19 ****
#define do_div(n,base) ({ \
! int __res; \
! __res = ((unsigned long) n) % (unsigned) base; \
! n = ((unsigned long) n) / (unsigned) base; \
__res; })
--- 13,18 ----
#define do_div(n,base) ({ \
! int __res = n % ((unsigned int) base); \
! n /= (unsigned int) base; \
__res; })
|
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From: <joe...@us...> - 2003-03-11 21:52:40
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv27530/arch/xtensa Modified Files: config.in Log Message: Add string "KGDB". I suspect more people will recognize "KGDB" than "Enable remote debugging". Index: config.in =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/config.in,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** config.in 25 Oct 2002 20:52:17 -0000 1.4 --- config.in 11 Mar 2003 21:52:33 -0000 1.5 *************** *** 191,195 **** bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ ! bool 'Enable remote debugging' CONFIG_KGDB endmenu --- 191,195 ---- bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ ! bool 'Enable remote debugging (KGDB)' CONFIG_KGDB endmenu |
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From: <joe...@us...> - 2003-03-11 21:14:22
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv8955/arch/xtensa/mm
Modified Files:
mmu.c
Log Message:
Add the last DTLB way to the dump structure.
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** mmu.c 11 Mar 2003 19:16:56 -0000 1.8
--- mmu.c 11 Mar 2003 21:14:17 -0000 1.9
***************
*** 340,343 ****
--- 340,348 ----
XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF)
+ },
+ { XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES),
+ XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES_LOG2),
+ XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, PAGESZ_LOG2_MIN),
+ XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ARF)
}
};
|
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From: <joe...@us...> - 2003-03-11 19:17:31
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv18775/arch/xtensa/mm
Modified Files:
mmu.c
Log Message:
Replace the 'iitlba' and 'idtlba' instructions (though disable the replacement for now). Various code improvements based on recent core.h additions. Answer and remove several XTFIXME comments.
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** mmu.c 5 Mar 2003 17:57:45 -0000 1.7
--- mmu.c 11 Mar 2003 19:16:56 -0000 1.8
***************
*** 22,35 ****
! /* Called from arch-indep. files: */
void flush_tlb_all (void)
{
unsigned long flags;
save_and_cli (flags);
__asm__ __volatile__ ("iitlba\n\t"
"idtlba\n\t"
"isync\n\t"); /* isync includes dsync */
restore_flags (flags);
}
--- 22,66 ----
! static inline void xtensa_flush_all_itlb (void)
! {
! int way, index;
!
! for (way = 0; way < XCHAL_ITLB_ARF_WAYS; way++) {
! for (index = 0; index < ITLB_ENTRIES_PER_ARF_WAY; index++) {
! int entry = way + (index << PAGE_SHIFT);
! invalidate_itlb_entry_no_isync (entry);
! }
! }
! asm volatile ("isync\n");
! }
!
! static inline void xtensa_flush_all_dtlb (void)
! {
! int way, index;
!
! for (way = 0; way < XCHAL_DTLB_ARF_WAYS; way++) {
! for (index = 0; index < DTLB_ENTRIES_PER_ARF_WAY; index++) {
! int entry = way + (index << PAGE_SHIFT);
! invalidate_dtlb_entry_no_isync (entry);
! }
! }
! asm volatile ("isync\n");
! }
+ /* Called from arch-indep. files: */
+
void flush_tlb_all (void)
{
unsigned long flags;
save_and_cli (flags);
+ #if 1
__asm__ __volatile__ ("iitlba\n\t"
"idtlba\n\t"
"isync\n\t"); /* isync includes dsync */
+ #else
+ xtensa_flush_all_itlb();
+ xtensa_flush_all_dtlb();
+ #endif
restore_flags (flags);
}
***************
*** 65,69 ****
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
! if (size <= NTLB_ENTRIES) {
int oldpid = get_rasid_register();
set_rasid_register (ASID_INSERT(mm->context));
--- 96,100 ----
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
! if (size <= SMALLEST_NTLB_ENTRIES) {
int oldpid = get_rasid_register();
set_rasid_register (ASID_INSERT(mm->context));
***************
*** 210,280 ****
- /* ** WARNING ** Before enabling XT2000_MMU_DUMP debugging, ensure the
- ** xtlb[i].indicies values are correct. We do not (yet) retrieve
- ** that information from the CHAL. */
-
#define XT2000_MMU_DUMP 1
#if (XT2000_MMU_DUMP == 1)
- /* XTFIXME: All of the values in the way_config_t tables should
- * somehow come from the CHAL. The hard-coded numbers reflect a
- * T1050 version with 8 entries per autorefill way. */
-
- #define _ITLB_INDICIES_PER_ARF_WAY 8
- #define _DTLB_INDICIES_PER_ARF_WAY 8
-
#define USE_ITLB 0
#define USE_DTLB 1
- #define WAY_TYPE_AUTOREFILL 0
- #define WAY_TYPE_STATIC 1
- #define WAY_TYPE_WIRED 2
-
struct way_config_t {
int indicies;
int indicies_log2;
int pgsz_log2;
! int type;
};
static struct way_config_t itlb[XCHAL_ITLB_WAYS] =
{
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 4, 2, 20, WAY_TYPE_WIRED },
! { 2, 1, 27, WAY_TYPE_STATIC },
! { 2, 1, 28, WAY_TYPE_STATIC }
};
static struct way_config_t dtlb[XCHAL_DTLB_WAYS] =
{
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 8, 3, 12, WAY_TYPE_AUTOREFILL },
! { 4, 2, 20, WAY_TYPE_WIRED },
! { 2, 1, 27, WAY_TYPE_STATIC },
! { 2, 1, 28, WAY_TYPE_STATIC },
! { 1, 0, 12, WAY_TYPE_WIRED },
! { 1, 0, 12, WAY_TYPE_WIRED },
! { 1, 0, 12, WAY_TYPE_WIRED }
};
! static char *way_type (int type)
{
! static char autorefill_str[] = "autorefill";
! static char static_str[] = "static";
! static char wired_str[] = "wired";
! static char unknown_str[] = "unknown";
!
! switch (type) {
! case WAY_TYPE_AUTOREFILL: return autorefill_str;
! case WAY_TYPE_WIRED: return wired_str;
! case WAY_TYPE_STATIC: return static_str;
! default: return unknown_str;
! }
}
--- 241,349 ----
#define XT2000_MMU_DUMP 1
#if (XT2000_MMU_DUMP == 1)
#define USE_ITLB 0
#define USE_DTLB 1
struct way_config_t {
int indicies;
int indicies_log2;
int pgsz_log2;
! int arf;
};
static struct way_config_t itlb[XCHAL_ITLB_WAYS] =
{
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ARF)
! },
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ARF)
! },
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ARF)
! },
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ARF)
! },
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ARF)
! },
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ARF)
! },
! { XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES_LOG2),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, PAGESZ_LOG2_MIN),
! XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ARF)
! }
};
static struct way_config_t dtlb[XCHAL_DTLB_WAYS] =
{
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ARF)
! },
! { XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES_LOG2),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN),
! XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF)
! }
};
! static inline char *way_type (int type)
{
! return type ? "autorefill" : "non-autorefill";
}
***************
*** 327,331 ****
printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
way, itlb[way].indicies,
! itlb[way].pgsz_log2, way_type(itlb[way].type));
for (index = 0; index < itlb[way].indicies; index++) {
print_itlb_entry(&itlb[way], way, index);
--- 396,400 ----
printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
way, itlb[way].indicies,
! itlb[way].pgsz_log2, way_type(itlb[way].arf));
for (index = 0; index < itlb[way].indicies; index++) {
print_itlb_entry(&itlb[way], way, index);
***************
*** 343,347 ****
printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
way, dtlb[way].indicies,
! dtlb[way].pgsz_log2, way_type(dtlb[way].type));
for (index = 0; index < dtlb[way].indicies; index++) {
print_dtlb_entry(&dtlb[way], way, index);
--- 412,416 ----
printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
way, dtlb[way].indicies,
! dtlb[way].pgsz_log2, way_type(dtlb[way].arf));
for (index = 0; index < dtlb[way].indicies; index++) {
print_dtlb_entry(&dtlb[way], way, index);
|
|
From: <joe...@us...> - 2003-03-11 19:17:10
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv18775/include/asm-xtensa
Modified Files:
assume.h mmu_context.h pgtable.h
Log Message:
Replace the 'iitlba' and 'idtlba' instructions (though disable the replacement for now). Various code improvements based on recent core.h additions. Answer and remove several XTFIXME comments.
Index: assume.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/assume.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** assume.h 28 Feb 2003 01:53:10 -0000 1.4
--- assume.h 11 Mar 2003 19:16:58 -0000 1.5
***************
*** 21,26 ****
! #if (XCHAL_HAVE_MMU != 1)
#error Linux must have an MMU!
#endif
--- 21,45 ----
! #if (XCHAL_HAVE_TLBS != 1)
#error Linux must have an MMU!
+ #endif
+
+ #if ((XCHAL_ITLB_ARF_WAYS == 0) || (XCHAL_DTLB_ARF_WAYS == 0))
+ #error MMU must have auto-refill ways
+ #endif
+
+ /* Linux was ported to Xtensa assuming all auto-refill ways in set 0
+ had the same properties (a very likely assumption). Multiple sets
+ of auto-refill ways will still work properly, but not as optimally
+ as the Xtensa designer may have assumed.
+
+ We make this case a hard #error, killing the kernel build, to alert
+ the developer to this condition (which is more likely an error).
+ You super-duper clever developers can change it to a warning or
+ remove it altogether if you think you know what you're doing. :)
+ */
+
+ #if ((XCHAL_ITLB_ARF_SETS != 1) || (XCHAL_DTLB_ARF_SETS != 1))
+ #error Linux may not use all auto-refill ways as efficiently as you think
#endif
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/mmu_context.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** mmu_context.h 15 Feb 2003 02:02:40 -0000 1.4
--- mmu_context.h 11 Mar 2003 19:17:00 -0000 1.5
***************
*** 25,43 ****
! /* NTLB_ENTRIES defines the number of auto-refill tlb entries in the
! itlb. Function flush_tlb_range() assumes that the dtlb has the
! same number and just uses NTLB_ENTRIES for both tlbs. */
! /* XTFIXME: INDICES_PER_ARG_WAY is a parameter exposed on the GUI.
! This information really should be available from the CHAL. Current
! values are either 4 or 8. An incorrect setting results is simply
! suboptimal, not incorrect. */
! #define INDICIES_PER_ARF_WAY 4
! #define NTLB_ENTRIES (XCHAL_ITLB_ARF_WAYS * INDICIES_PER_ARF_WAY)
! #if (XCHAL_ITLB_ARF_WAYS != XCHAL_DTLB_ARF_WAYS)
! #error flush_tlb_range() assumes an equal number of ways in itlb and dtlb.
#endif
/* asid_cache tracks only the ASID[USER_RING] field of the RASID
--- 25,50 ----
! /* Define the number of entries per auto-refill way in set 0 of both I
! and D TLBs. We deal only with set 0 here (an assumption further
! explained in assume.h). Also, define the total number of ARF
! entries in both TLBs. */
! #define ITLB_ENTRIES_PER_ARF_WAY (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES))
! #define DTLB_ENTRIES_PER_ARF_WAY (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES))
! #define ITLB_ENTRIES (ITLB_ENTRIES_PER_ARF_WAY * (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,WAYS)))
! #define DTLB_ENTRIES (DTLB_ENTRIES_PER_ARF_WAY * (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,WAYS)))
!
! /* SMALLEST_NTLB_ENTRIES is the smaller of ITLB_ENTRIES and
! DTLB_ENTRIES. In practice, they are probably equal. This macro
! simplifies function flush_tlb_range(). */
!
! #if (DTLB_ENTRIES < ITLB_ENTRIES)
! #define SMALLEST_NTLB_ENTRIES DTLB_ENTRIES
! #else
! #define SMALLEST_NTLB_ENTRIES ITLB_ENTRIES
#endif
+
/* asid_cache tracks only the ASID[USER_RING] field of the RASID
Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** pgtable.h 5 Mar 2003 17:57:46 -0000 1.9
--- pgtable.h 11 Mar 2003 19:17:00 -0000 1.10
***************
*** 25,29 ****
#include <linux/linkage.h>
#include <linux/config.h>
- #include <linux/mm.h>
--- 25,28 ----
***************
*** 35,49 ****
#if XTENSA_CACHE_ALIAS
- /* We provide our own get_unmapped_area to avoid cache alias issue */
- #define HAVE_ARCH_UNMAPPED_AREA
- #define PG_mapped PG_arch_1
! /* this is a mask of the naughty bits that can cause cache aliasing
! * problems. Because xtensa has a configurable cache size we have to
! * get funky.... Start with 0xffff_ffff and then mask off everything
! * else that is not a problem...
! */
! #define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
! #define XT_CACHE_ALIAS_BITS (( (-1) & ~(PAGE_SIZE-1)) & (XT_CACHE_WAYSIZE-1))
#endif
--- 34,50 ----
#if XTENSA_CACHE_ALIAS
! /* We provide our own get_unmapped_area to avoid cache alias issue */
! #define HAVE_ARCH_UNMAPPED_AREA
! #define PG_mapped PG_arch_1
!
! /* this is a mask of the naughty bits that can cause cache aliasing
! * problems. Because xtensa has a configurable cache size we have to
! * get funky.... Start with 0xffff_ffff and then mask off everything
! * else that is not a problem...
! */
! #define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
! #define XT_CACHE_ALIAS_BITS (( (-1) & ~(PAGE_SIZE-1)) & (XT_CACHE_WAYSIZE-1))
!
#endif
***************
*** 83,95 ****
/* 19feb2003 -- jn
! * enabling dcache aliasing, have fear....
*/
#if XTENSA_CACHE_ALIAS
! void flush_dcache_page(struct page *page);
// void xtensa_cache_init(void);
#else
! #define flush_dcache_page(page) do { } while (0)
! // #define xtensa_cache_init() do { } while (0)
#endif
--- 84,97 ----
/* 19feb2003 -- jn
! * enabling dcache aliasing
*/
#if XTENSA_CACHE_ALIAS
! void flush_dcache_page(struct page *page);
// void xtensa_cache_init(void);
+
#else
! #define flush_dcache_page(page) do { } while (0)
! // #define xtensa_cache_init() do { } while (0)
#endif
***************
*** 98,113 ****
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
! /* Basically we have the same two-level (which is the logical three level
! * Linux page table layout folded) page tables as the i386.
*/
! /* XTFIXME: Need to pull the following constant from the CHAL, if possible. */
! #define WIRED_WAY_FOR_PAGE_TABLE 7
- /* 27feb2003 -- jn
- * I am hijacking way9 of the dtlb for the copy_user_page and clear_user_page
- * functions.
- */
- #define WIRED_WAY_FOR_COPY_USER_PAGE 9
--- 100,126 ----
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
! /* Basically we have the same two-level (which is the logical three
! * level Linux page table layout folded) page tables as the i386. Use
! * the first min-wired way for mapping page-table pages. Page
! * coloring requires a second min-wired way.
*/
! #if (XCHAL_DTLB_MINWIRED_SETS == 0)
! #error Need a min-wired way for mapping page-table pages
! #endif
!
! #define _FIRST_MIN_WIRED XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAY)
! #define _MIN_WIRED_COUNT XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAYS)
!
! #define WIRED_WAY_FOR_PAGE_TABLE _FIRST_MIN_WIRED
!
! #if XTENSA_CACHE_ALIAS
! # if (_MIN_WIRED_COUNT >= 2)
! # define WIRED_WAY_FOR_COPY_USER_PAGE (_FIRST_MIN_WIRED + 1)
! # else
! # error Page coloring requires its own min-wired dtlb way
! # endif
! #endif
***************
*** 131,156 ****
#define FIRST_USER_PGD_NR 0
! /* 27feb2003 -- jn
! * When caches are aliasable, we need to reserve a small portion of
! * virtual space for copy_user_page, and clear_user_page. This is
! * used to reduce the amount of cache flushing required.
! */
!
! /*
! * XTFIXME: The CHAL should provide memory-map info on local memories and
! * XLMI ports that are identity mapped. They are typically located just
! * below the kernel space at 0xD0000000, and they are relatively small
! * (today). We want to verify (with #error directives), however, that
! * these memory-mapped processor features do not overlap the VMALLOC space
! * we define here. [Sep 11, 2002]
*/
- /* 0xC0000000-0xC8000000 reserved for vmalloc; below allows guard memory */
#if (XTENSA_CACHE_ALIAS)
! #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
! #define XTENSA_ALIAS_RESERVE_START 0xC0010000
! #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
#else
! #define VMALLOC_START 0xC0010000
#endif
--- 144,163 ----
#define FIRST_USER_PGD_NR 0
! /* 27feb2003 -- jn
! *
! * 0xC0000000-0xC8000000 reserved for kernel vmalloc. See also
! * assume.h. When caches are aliasable, we need to reserve a small
! * portion of virtual space for copy_user_page, and clear_user_page.
! * This is used to reduce the amount of cache flushing required.
*/
#if (XTENSA_CACHE_ALIAS)
!
! #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
! #define XTENSA_ALIAS_RESERVE_START 0xC0010000
! #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
!
#else
! #define VMALLOC_START 0xC0010000
#endif
***************
*** 609,613 ****
/* TLB operations. */
- /* XTFIXME: The following constants should come from the CHAL. */
#define ITLB_WAYS_LOG2 XCHAL_ITLB_WAY_BITS
#define DTLB_WAYS_LOG2 XCHAL_DTLB_WAY_BITS
--- 616,619 ----
***************
*** 662,665 ****
--- 668,690 ----
"dsync\n\t"
: : "a" (probe));
+ }
+
+ /* Use the .._no_isync functions with caution. Generally, these are
+ * handy for bulk invalidates followed by a single 'isync'. The
+ * caller must follow up with an 'isync', which can be relatively
+ * expensive on some Xtensa implementations. */
+
+ extern inline void invalidate_itlb_entry_no_isync (unsigned entry)
+ {
+ /* Caller must follow up with 'isync'. */
+ asm volatile ("iitlb %0\n"
+ : : "a" (entry) );
+ }
+
+ extern inline void invalidate_dtlb_entry_no_isync (unsigned entry)
+ {
+ /* Caller must follow up with 'isync'. */
+ asm volatile ("idtlb %0\n"
+ : : "a" (entry) );
}
|
|
From: <joe...@us...> - 2003-03-11 19:09:46
|
Update of /cvsroot/xtensa/linux/arch/xtensa/boot/boot-redboot In directory sc8-pr-cvs1:/tmp/cvs-serv17157/arch/xtensa/boot/boot-redboot Modified Files: bootstrap.S Log Message: Documentation change only (answering an XTFIXME concern). Index: bootstrap.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/boot/boot-redboot/bootstrap.S,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** bootstrap.S 1 Mar 2003 03:02:46 -0000 1.2 --- bootstrap.S 11 Mar 2003 19:09:40 -0000 1.3 *************** *** 66,70 **** /* copy the loader to its address */ ! /* XTFIXME workaround (bug in assembler: addi a0, a0, ... doesn't work) */ addi a4, a0, __start - __start_a0 --- 66,71 ---- /* copy the loader to its address */ ! /* Note: The assembler cannot relax "addi a0, a0, ..." to an ! l32r, so we load to a4 first. */ addi a4, a0, __start - __start_a0 |
|
From: <joe...@us...> - 2003-03-10 19:01:06
|
Update of /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000
In directory sc8-pr-cvs1:/tmp/cvs-serv13294/arch/xtensa/platform-xt2000
Modified Files:
setup.c
Log Message:
Set LED to something more appropriate than leftover RedBoot messages.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/platform-xt2000/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** setup.c 2 Dec 2002 20:32:29 -0000 1.3
--- setup.c 10 Mar 2003 19:00:58 -0000 1.4
***************
*** 107,110 ****
--- 107,112 ----
mach_halt = xt2000_halt;
mach_power_off = xt2000_power_off;
+
+ led_print ("LINUX ");
}
|
|
From: <joe...@us...> - 2003-03-07 19:15:59
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le
In directory sc8-pr-cvs1:/tmp/cvs-serv31823/include/asm-xtensa/xtensa/config-linux_le
Modified Files:
core.h defs.h specreg.h system.h
Added Files:
tie.h
Log Message:
Update config-specific files with later versions. Removes the NSA/NSAU option from the baseline configs, corrects copyright info, and adds more macros to improve kernel implementation.
--- NEW FILE: tie.h ---
/*
* xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration,
* and furthermore for a specific set of TIE source files that extend
* basic core functionality.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_CONFIG_TIE_H
#define XTENSA_CONFIG_TIE_H
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_CP_NUM 0 /* number of coprocessors */
#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 0
#define XCHAL_EXTRA_SA_ALIGN 1
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 1
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
.endm
#endif /*_ASMLANGUAGE*/
/*
* Contents of save areas in terms of libdb register numbers.
* NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
* it is up to the user of this header file to define these macros
* usefully before each expansion of the CONTENTS_LIBDB macros.
* (Fields rsv[123] are reserved for future additions; they are currently
* set to zero but may be set to some useful values in the future.)
*
* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
*/
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#if 0 /* is there something equivalent for user TIE? */
#define XCHAL_CORE_ID "linux_le" /* configuration's alphanumeric core identifier
(CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x000066FD /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC10FD3FE /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x008066FD /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
#endif /*0*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#endif /*0*/
#endif /*XTENSA_CONFIG_TIE_H*/
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/core.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** core.h 7 Feb 2003 02:03:34 -0000 1.3
--- core.h 7 Mar 2003 19:15:19 -0000 1.4
***************
*** 11,20 ****
/*
! * Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 11,35 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
***************
*** 434,438 ****
/*
! * Level-1 Exception Causes:
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
--- 449,455 ----
/*
! * General Exception Causes
! * (values of EXCCAUSE special register set by general exceptions,
! * which vector to the user, kernel, or double-exception vectors):
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
***************
*** 491,652 ****
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
- #define XCHAL_CP_NUM 0 /* number of coprocessors */
- #define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
- #define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
-
- /* Space for coprocessors' state save areas: */
- #define XCHAL_CP0_SA_SIZE 0
- #define XCHAL_CP1_SA_SIZE 0
- #define XCHAL_CP2_SA_SIZE 0
- #define XCHAL_CP3_SA_SIZE 0
- #define XCHAL_CP4_SA_SIZE 0
- #define XCHAL_CP5_SA_SIZE 0
- #define XCHAL_CP6_SA_SIZE 0
- #define XCHAL_CP7_SA_SIZE 0
- /* Minimum required alignments of CP state save areas: */
- #define XCHAL_CP0_SA_ALIGN 1
- #define XCHAL_CP1_SA_ALIGN 1
- #define XCHAL_CP2_SA_ALIGN 1
- #define XCHAL_CP3_SA_ALIGN 1
- #define XCHAL_CP4_SA_ALIGN 1
- #define XCHAL_CP5_SA_ALIGN 1
- #define XCHAL_CP6_SA_ALIGN 1
- #define XCHAL_CP7_SA_ALIGN 1
-
- /* Indexing macros: */
- #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
- #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
- #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
- #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
-
-
- /* Space for "extra" state (user special registers and non-cp TIE) save area: */
- #define XCHAL_EXTRA_SA_SIZE 0
- #define XCHAL_EXTRA_SA_ALIGN 1
-
- /* Total save area size (extra + all coprocessors) */
- /* (not useful until xthal_{save,restore}_all_extra() is implemented, */
- /* but included for Tor2 beta; doesn't account for alignment!): */
- #define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
-
- /* Combined required alignment for all CP and EXTRA state save areas */
- /* (does not include required alignment for any base config registers): */
- #define XCHAL_CPEXTRA_SA_ALIGN 1
-
- /* ... */
-
-
- #ifdef _ASMLANGUAGE
- /*
- * Assembly-language specific definitions (assembly macros, etc.).
- */
- #include <xtensa/config/specreg.h>
-
- /********************
- * Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
- */
-
- /* (none) */
-
-
- /********************
- * Macros to create functions that save and restore all EXTRA (non-coprocessor) state
- * (does not include zero-overhead loop registers and non-optional registers).
- */
-
- /*
- * Macro that expands to the body of a function that
- * stores the extra (non-coprocessor) optional/custom state.
- * Entry: a2 = ptr to save area in which to save extra state
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_extra_store_funcbody
- .endm
-
-
- /*
- * Macro that expands to the body of a function that
- * loads the extra (non-coprocessor) optional/custom state.
- * Entry: a2 = ptr to save area from which to restore extra state
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_extra_load_funcbody
- .endm
-
-
- /********************
- * Macros to save and restore the state of each TIE coprocessor.
- */
-
-
-
- /********************
- * Macros to create functions that save and restore the state of *any* TIE coprocessor.
- */
-
- /*
- * Macro that expands to the body of a function
- * that stores the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area in which to save cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_store_funcbody
- .endm
-
-
- /*
- * Macro that expands to the body of a function
- * that loads the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area from which to restore cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_load_funcbody
- .endm
-
- #endif /*_ASMLANGUAGE*/
-
! /*
! * Contents of save areas in terms of libdb register numbers.
! * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
! * it is up to the user of this header file to define these macros
! * usefully before each expansion of the CONTENTS_LIBDB macros.
! * (Fields rsv[123] are reserved for future additions; they are currently
! * set to zero but may be set to some useful values in the future.)
! *
! * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
! * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
! * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
! */
!
! #define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
!
! #define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
- #define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
--- 508,515 ----
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
! #include <xtensa/config/tie.h>
***************
*** 657,664 ****
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
! #define XCHAL_NUM_INSTRAM 1 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
! #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs configured */
! #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
--- 520,527 ----
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
! #define XCHAL_NUM_INSTRAM 0 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
! #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs configured */
! #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
***************
*** 666,690 ****
#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
- /* Instruction RAM 0: */
- #define XCHAL_INSTRAM0_VADDR 0xCFFFF000
- #define XCHAL_INSTRAM0_PADDR 0xCFFFF000
- #define XCHAL_INSTRAM0_SIZE 4096
- #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
- #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
- #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
-
- /* Data RAM 0: */
- #define XCHAL_DATARAM0_VADDR 0xCFFFE000
- #define XCHAL_DATARAM0_PADDR 0xCFFFE000
- #define XCHAL_DATARAM0_SIZE 2048
- #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
- #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
- #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
-
- /* XLMI Port 0: */
- #define XCHAL_XLMI0_VADDR 0xCFF80000
- #define XCHAL_XLMI0_PADDR 0xCFF80000
- #define XCHAL_XLMI0_SIZE 262144
-
--- 529,532 ----
***************
*** 795,801 ****
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
- */
! /* MMU okay: yes */
/*----------------------------------------------------------------------
--- 637,644 ----
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
! MMU okay: yes
! */
!
/*----------------------------------------------------------------------
***************
*** 803,806 ****
--- 646,693 ----
----------------------------------------------------------------------*/
+ /*
+ * General notes on MMU parameters.
+ *
+ * Terminology:
+ * ASID = address-space ID (acts as an "extension" of virtual addresses)
+ * VPN = virtual page number
+ * PPN = physical page number
+ * CA = encoded cache attribute (access modes)
+ * TLB = translation look-aside buffer (term is stretched somewhat here)
+ * I = instruction (fetch accesses)
+ * D = data (load and store accesses)
+ * way = each TLB (ITLB and DTLB) consists of a number of "ways"
+ * that simultaneously match the virtual address of an access;
+ * a TLB successfully translates a virtual address if exactly
+ * one way matches the vaddr; if none match, it is a miss;
+ * if multiple match, one gets a "multihit" exception;
+ * each way can be independently configured in terms of number of
+ * entries, page sizes, which fields are writable or constant, etc.
+ * set = group of contiguous ways with exactly identical parameters
+ * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
+ * from the page table and storing it in one of the auto-refill ways;
+ * if this PTE load also misses, a miss exception is posted for s/w.
+ * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ * page arbitrarily under program control; it has a single entry,
+ * is non-auto-refill (some other way(s) must be auto-refill),
+ * all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ * restriction is that this be the only page size it supports).
+ *
+ * TLB way entries are virtually indexed.
+ * TLB ways that support multiple page sizes:
+ * - must have all writable VPN and PPN fields;
+ * - can only use one page size at any given time (eg. setup at startup),
+ * selected by the respective ITLBCFG or DTLBCFG special register,
+ * whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ * this list may be sparse for auto-refill ways because auto-refill
+ * ways have independent lists of supported page sizes sharing a
+ * common encoding with PTE entries; the encoding is the index into
+ * this list; unsupported sizes for a given way are zero in the list;
+ * selecting unsupported sizes results in undefined hardware behaviour;
+ * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
***************
*** 818,835 ****
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
! #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure */
! #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure */
- /* Instruction TLB: */
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
! #define XCHAL_ITLB_WAYS 7 /* number of ways */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
- /* Data TLB: */
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
! #define XCHAL_DTLB_WAYS 10 /* number of ways */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
- /* ... */
/*
--- 705,1022 ----
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
! #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
! #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
!
!
! /*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
! #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
+ #define XCHAL_ITLB_SETS 4 /* number of sets (groups of ways with identical settings) */
+
+ /* Way set to which each way belongs: */
+ #define XCHAL_ITLB_WAY0_SET 0
+ #define XCHAL_ITLB_WAY1_SET 0
+ #define XCHAL_ITLB_WAY2_SET 0
+ #define XCHAL_ITLB_WAY3_SET 0
+ #define XCHAL_ITLB_WAY4_SET 1
+ #define XCHAL_ITLB_WAY5_SET 2
+ #define XCHAL_ITLB_WAY6_SET 3
+
+ /* Ways sets that are used by hardware auto-refill (ARF): */
+ #define XCHAL_ITLB_ARF_SETS 1 /* number of auto-refill sets */
+ #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
+
+ /* Way sets that are "min-wired" (see terminology comment above): */
+ #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
+
+
+ /* ITLB way set 0 (group of ways 0 thru 3): */
+ #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* ITLB way set 1 (group of ways 4 thru 4): */
+ #define XCHAL_ITLB_SET1_WAY 4 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* ITLB way set 2 (group of ways 5 thru 5): */
+ #define XCHAL_ITLB_SET2_WAY 5 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_ASID_CONST 0x01
+ #define XCHAL_ITLB_SET2_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_VPN_CONST 0xD0000000
+ #define XCHAL_ITLB_SET2_E1_VPN_CONST 0xD8000000
+ /* Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_PPN_CONST 0x00000000
+ #define XCHAL_ITLB_SET2_E1_PPN_CONST 0x00000000
+ /* Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_CA_CONST 0x07
+ #define XCHAL_ITLB_SET2_E1_CA_CONST 0x03
+
+ /* ITLB way set 3 (group of ways 6 thru 6): */
+ #define XCHAL_ITLB_SET3_WAY 6 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_ASID_CONST 0x01
+ #define XCHAL_ITLB_SET3_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_VPN_CONST 0xE0000000
+ #define XCHAL_ITLB_SET3_E1_VPN_CONST 0xF0000000
+ /* Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_PPN_CONST 0xF0000000
+ #define XCHAL_ITLB_SET3_E1_PPN_CONST 0xF0000000
+ /* Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_CA_CONST 0x07
+ #define XCHAL_ITLB_SET3_E1_CA_CONST 0x03
+
+ /* Indexing macros: */
+ #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
+ #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
+ #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
+ #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
+ /*
+ * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+
+ /*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
! #define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
+ #define XCHAL_DTLB_SETS 5 /* number of sets (groups of ways with identical settings) */
+
+ /* Way set to which each way belongs: */
+ #define XCHAL_DTLB_WAY0_SET 0
+ #define XCHAL_DTLB_WAY1_SET 0
+ #define XCHAL_DTLB_WAY2_SET 0
+ #define XCHAL_DTLB_WAY3_SET 0
+ #define XCHAL_DTLB_WAY4_SET 1
+ #define XCHAL_DTLB_WAY5_SET 2
+ #define XCHAL_DTLB_WAY6_SET 3
+ #define XCHAL_DTLB_WAY7_SET 4
+ #define XCHAL_DTLB_WAY8_SET 4
+ #define XCHAL_DTLB_WAY9_SET 4
+
+ /* Ways sets that are used by hardware auto-refill (ARF): */
+ #define XCHAL_DTLB_ARF_SETS 1 /* number of auto-refill sets */
+ #define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
+
+ /* Way sets that are "min-wired" (see terminology comment above): */
+ #define XCHAL_DTLB_MINWIRED_SETS 1 /* number of "min-wired" sets */
+ #define XCHAL_DTLB_MINWIRED_SET0 4 /* index of n'th "min-wired" set */
+
+
+ /* DTLB way set 0 (group of ways 0 thru 3): */
+ #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* DTLB way set 1 (group of ways 4 thru 4): */
+ #define XCHAL_DTLB_SET1_WAY 4 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* DTLB way set 2 (group of ways 5 thru 5): */
+ #define XCHAL_DTLB_SET2_WAY 5 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_ASID_CONST 0x01
+ #define XCHAL_DTLB_SET2_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_VPN_CONST 0xD0000000
+ #define XCHAL_DTLB_SET2_E1_VPN_CONST 0xD8000000
+ /* Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_PPN_CONST 0x00000000
+ #define XCHAL_DTLB_SET2_E1_PPN_CONST 0x00000000
+ /* Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_CA_CONST 0x07
+ #define XCHAL_DTLB_SET2_E1_CA_CONST 0x03
+
+ /* DTLB way set 3 (group of ways 6 thru 6): */
+ #define XCHAL_DTLB_SET3_WAY 6 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_ASID_CONST 0x01
+ #define XCHAL_DTLB_SET3_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_VPN_CONST 0xE0000000
+ #define XCHAL_DTLB_SET3_E1_VPN_CONST 0xF0000000
+ /* Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_PPN_CONST 0xF0000000
+ #define XCHAL_DTLB_SET3_E1_PPN_CONST 0xF0000000
+ /* Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_CA_CONST 0x07
+ #define XCHAL_DTLB_SET3_E1_CA_CONST 0x03
+
+ /* DTLB way set 4 (group of ways 7 thru 9): */
+ #define XCHAL_DTLB_SET4_WAY 7 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET4_WAYS 3 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET4_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET4_ENTRIES 1 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET4_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET4_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* Indexing macros: */
+ #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
+ #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
+ #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
+ #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
+ /*
+ * Example use: XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
/*
***************
*** 1000,1007 ****
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
- #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
! #define XCHAL_HAVE_NSA 1 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
--- 1187,1193 ----
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
! #define XCHAL_HAVE_NSA 0 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
***************
*** 1009,1023 ****
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
- #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
- #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
- #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
! #define XCHAL_HAVE_PRID 1 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
--- 1195,1212 ----
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
! #define XCHAL_HAVE_PRID 0 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
+
+ /* These relate a bit more to TIE: */
+ #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
+ #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
Index: defs.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/defs.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** defs.h 23 Oct 2002 20:53:21 -0000 1.1
--- defs.h 7 Mar 2003 19:15:20 -0000 1.2
***************
*** 2,11 ****
/*
! * Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 2,26 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
***************
*** 205,233 ****
- #define NSA_ASM(arr, ars) {\
- __asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
- }
-
- #define XT_NSA(ars) \
- ({ \
- unsigned _arr; \
- int _ars = ars; \
- NSA_ASM(_arr, _ars); \
- _arr; \
- })
-
- #define NSAU_ASM(arr, ars) {\
- __asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
- }
-
- #define XT_NSAU(ars) \
- ({ \
- unsigned _arr; \
- unsigned _ars = ars; \
- NSAU_ASM(_arr, _ars); \
- _arr; \
- })
-
-
#endif /* __GNUC__ && !__XCC__ */
--- 220,223 ----
***************
*** 274,282 ****
#define XT_SSAI _TIE_SSAI
- /* Miscellaneous instructions */
- extern unsigned _TIE_NSA(int ars);
- extern unsigned _TIE_NSAU(unsigned ars);
- #define XT_NSA _TIE_NSA
- #define XT_NSAU _TIE_NSAU
#endif /* __XCC__ */
--- 264,267 ----
Index: specreg.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/specreg.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** specreg.h 23 Oct 2002 20:53:21 -0000 1.1
--- specreg.h 7 Mar 2003 19:15:21 -0000 1.2
***************
*** 6,15 ****
/*
! * Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 6,30 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
***************
*** 58,62 ****
#define DEBUGCAUSE 233
#define CCOUNT 234
- #define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
--- 73,76 ----
Index: system.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/system.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** system.h 23 Oct 2002 20:53:21 -0000 1.1
--- system.h 7 Mar 2003 19:15:21 -0000 1.2
***************
*** 12,21 ****
/*
! * Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 12,36 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
***************
*** 48,63 ****
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
- #if 0
- #define XSHAL_ETHER_VADDR 0xFD030000
- #define XSHAL_ETHER_PADDR 0xFD030000
- #define XSHAL_UART_VADDR 0xFD050000
- #define XSHAL_UART_PADDR 0xFD050000
- #define XSHAL_LED_VADDR 0xFD040000
- #define XSHAL_LED_PADDR 0xFD040000
- #define XSHAL_FLASH_VADDR 0xF8000000
- #define XSHAL_FLASH_PADDR 0xF8000000
- #define XSHAL_FLASH_SIZE 0x04000000
- #endif /*0*/
-
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
--- 63,66 ----
***************
*** 92,96 ****
/* Alternate system RAM (different device than system RAM): */
! #define XSHAL_ALTRAM_VADDR 0xCFA00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
--- 95,99 ----
/* Alternate system RAM (different device than system RAM): */
! #define XSHAL_ALTRAM_VADDR 0xCEE00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
***************
*** 98,113 ****
/*----------------------------------------------------------------------
! DEVICE-ADDRESS DEPENDENT...
----------------------------------------------------------------------*/
/*
! * Values written to CACHEATTR special register (or its equivalent)
! * to enable and disable caches in various modes:
*/
! #define XSHAL_CACHEATTR_WRITEBACK 0x22FFFFF1 /* enable caches in write-back mode */
! #define XSHAL_CACHEATTR_WRITEALLOC 0x22FFFFF1 /* enable caches in write-allocate mode */
! #define XSHAL_CACHEATTR_WRITETHRU 0x22FFFFF1 /* enable caches in write-through mode */
! #define XSHAL_CACHEATTR_BYPASS 0x22FFFFF2 /* disable caches in bypass mode */
! #define XSHAL_CACHEATTR_DEFAULT XSHAL_CACHEATTR_WRITETHRU /* default setting to enable caches */
/*----------------------------------------------------------------------
--- 101,121 ----
/*----------------------------------------------------------------------
! * DEVICE-ADDRESS DEPENDENT...
! *
! * Values written to CACHEATTR special register (or its equivalent)
! * to enable and disable caches in various modes.
! *----------------------------------------------------------------------*/
!
! /*----------------------------------------------------------------------
! BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
! * NOTE: the following two macros are DEPRECATED. Use the latter
! * board-specific macros instead, which are specially tuned for the
! * particular ta...
[truncated message content] |
|
From: <joe...@us...> - 2003-03-07 19:15:56
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be
In directory sc8-pr-cvs1:/tmp/cvs-serv31823/include/asm-xtensa/xtensa/config-linux_be
Modified Files:
core.h defs.h specreg.h system.h
Added Files:
tie.h
Log Message:
Update config-specific files with later versions. Removes the NSA/NSAU option from the baseline configs, corrects copyright info, and adds more macros to improve kernel implementation.
--- NEW FILE: tie.h ---
/*
* xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration,
* and furthermore for a specific set of TIE source files that extend
* basic core functionality.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_CONFIG_TIE_H
#define XTENSA_CONFIG_TIE_H
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_CP_NUM 0 /* number of coprocessors */
#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 0
#define XCHAL_EXTRA_SA_ALIGN 1
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 1
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
.endm
#endif /*_ASMLANGUAGE*/
/*
* Contents of save areas in terms of libdb register numbers.
* NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
* it is up to the user of this header file to define these macros
* usefully before each expansion of the CONTENTS_LIBDB macros.
* (Fields rsv[123] are reserved for future additions; they are currently
* set to zero but may be set to some useful values in the future.)
*
* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
*/
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#if 0 /* is there something equivalent for user TIE? */
#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
(CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
#endif /*0*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#endif /*0*/
#endif /*XTENSA_CONFIG_TIE_H*/
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/core.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** core.h 7 Feb 2003 02:03:34 -0000 1.3
--- core.h 7 Mar 2003 19:15:16 -0000 1.4
***************
*** 1,24 ****
! /*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/core.h -- HAL definitions that are
! * dependent on CORE configuration.
! *
! * This header file is sometimes referred to as the "compile-time HAL"
! * or CHAL. It was generated for a specific Xtensa processor
! * configuration.
! *
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * It is perfectly normal, however, for the HAL source itself to
! * include this file.
*
! * This file is subject to the terms and conditions of the GNU General Public
! * License. See the file "COPYING" in the main directory of this archive
! * for more details.
*
! * Copyright (C) 1999 - 2003 Tensilica Inc.
*/
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
--- 1,38 ----
! /*
! * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
*
! * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
! * It was generated for a specific Xtensa processor configuration.
*
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * It is perfectly normal, however, for the HAL source itself to include this file.
! */
!
! /*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
+
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
***************
*** 435,439 ****
/*
! * Level-1 Exception Causes:
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
--- 449,455 ----
/*
! * General Exception Causes
! * (values of EXCCAUSE special register set by general exceptions,
! * which vector to the user, kernel, or double-exception vectors):
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
***************
*** 492,653 ****
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
- #define XCHAL_CP_NUM 0 /* number of coprocessors */
- #define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
- #define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
-
- /* Space for coprocessors' state save areas: */
- #define XCHAL_CP0_SA_SIZE 0
- #define XCHAL_CP1_SA_SIZE 0
- #define XCHAL_CP2_SA_SIZE 0
- #define XCHAL_CP3_SA_SIZE 0
- #define XCHAL_CP4_SA_SIZE 0
- #define XCHAL_CP5_SA_SIZE 0
- #define XCHAL_CP6_SA_SIZE 0
- #define XCHAL_CP7_SA_SIZE 0
- /* Minimum required alignments of CP state save areas: */
- #define XCHAL_CP0_SA_ALIGN 1
- #define XCHAL_CP1_SA_ALIGN 1
- #define XCHAL_CP2_SA_ALIGN 1
- #define XCHAL_CP3_SA_ALIGN 1
- #define XCHAL_CP4_SA_ALIGN 1
- #define XCHAL_CP5_SA_ALIGN 1
- #define XCHAL_CP6_SA_ALIGN 1
- #define XCHAL_CP7_SA_ALIGN 1
-
- /* Indexing macros: */
- #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
- #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
- #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
- #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
-
-
- /* Space for "extra" state (user special registers and non-cp TIE) save area: */
- #define XCHAL_EXTRA_SA_SIZE 0
- #define XCHAL_EXTRA_SA_ALIGN 1
-
- /* Total save area size (extra + all coprocessors) */
- /* (not useful until xthal_{save,restore}_all_extra() is implemented, */
- /* but included for Tor2 beta; doesn't account for alignment!): */
- #define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
-
- /* Combined required alignment for all CP and EXTRA state save areas */
- /* (does not include required alignment for any base config registers): */
- #define XCHAL_CPEXTRA_SA_ALIGN 1
-
- /* ... */
-
-
- #ifdef _ASMLANGUAGE
- /*
- * Assembly-language specific definitions (assembly macros, etc.).
- */
- #include <xtensa/config/specreg.h>
-
- /********************
- * Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
- */
-
- /* (none) */
-
-
- /********************
- * Macros to create functions that save and restore all EXTRA (non-coprocessor) state
- * (does not include zero-overhead loop registers and non-optional registers).
- */
-
- /*
- * Macro that expands to the body of a function that
- * stores the extra (non-coprocessor) optional/custom state.
- * Entry: a2 = ptr to save area in which to save extra state
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_extra_store_funcbody
- .endm
-
-
- /*
- * Macro that expands to the body of a function that
- * loads the extra (non-coprocessor) optional/custom state.
- * Entry: a2 = ptr to save area from which to restore extra state
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_extra_load_funcbody
- .endm
-
-
- /********************
- * Macros to save and restore the state of each TIE coprocessor.
- */
-
-
-
- /********************
- * Macros to create functions that save and restore the state of *any* TIE coprocessor.
- */
-
- /*
- * Macro that expands to the body of a function
- * that stores the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area in which to save cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_store_funcbody
- .endm
-
-
- /*
- * Macro that expands to the body of a function
- * that loads the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area from which to restore cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_load_funcbody
- .endm
-
- #endif /*_ASMLANGUAGE*/
-
-
- /*
- * Contents of save areas in terms of libdb register numbers.
- * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
- * it is up to the user of this header file to define these macros
- * usefully before each expansion of the CONTENTS_LIBDB macros.
- * (Fields rsv[123] are reserved for future additions; they are currently
- * set to zero but may be set to some useful values in the future.)
- *
- * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
- * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
- * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
- */
-
- #define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
! #define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
- #define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
--- 508,515 ----
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
! #include <xtensa/config/tie.h>
***************
*** 658,665 ****
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
! #define XCHAL_NUM_INSTRAM 1 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
! #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs configured */
! #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
--- 520,527 ----
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
! #define XCHAL_NUM_INSTRAM 0 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
! #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs configured */
! #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
***************
*** 667,691 ****
#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
- /* Instruction RAM 0: */
- #define XCHAL_INSTRAM0_VADDR 0xCFFFF000
- #define XCHAL_INSTRAM0_PADDR 0xCFFFF000
- #define XCHAL_INSTRAM0_SIZE 4096
- #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
- #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
- #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
-
- /* Data RAM 0: */
- #define XCHAL_DATARAM0_VADDR 0xCFFFE000
- #define XCHAL_DATARAM0_PADDR 0xCFFFE000
- #define XCHAL_DATARAM0_SIZE 2048
- #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
- #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
- #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
-
- /* XLMI Port 0: */
- #define XCHAL_XLMI0_VADDR 0xCFF80000
- #define XCHAL_XLMI0_PADDR 0xCFF80000
- #define XCHAL_XLMI0_SIZE 262144
-
--- 529,532 ----
***************
*** 796,802 ****
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
- */
! /* MMU okay: yes */
/*----------------------------------------------------------------------
--- 637,644 ----
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
! MMU okay: yes
! */
!
/*----------------------------------------------------------------------
***************
*** 804,807 ****
--- 646,693 ----
----------------------------------------------------------------------*/
+ /*
+ * General notes on MMU parameters.
+ *
+ * Terminology:
+ * ASID = address-space ID (acts as an "extension" of virtual addresses)
+ * VPN = virtual page number
+ * PPN = physical page number
+ * CA = encoded cache attribute (access modes)
+ * TLB = translation look-aside buffer (term is stretched somewhat here)
+ * I = instruction (fetch accesses)
+ * D = data (load and store accesses)
+ * way = each TLB (ITLB and DTLB) consists of a number of "ways"
+ * that simultaneously match the virtual address of an access;
+ * a TLB successfully translates a virtual address if exactly
+ * one way matches the vaddr; if none match, it is a miss;
+ * if multiple match, one gets a "multihit" exception;
+ * each way can be independently configured in terms of number of
+ * entries, page sizes, which fields are writable or constant, etc.
+ * set = group of contiguous ways with exactly identical parameters
+ * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
+ * from the page table and storing it in one of the auto-refill ways;
+ * if this PTE load also misses, a miss exception is posted for s/w.
+ * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ * page arbitrarily under program control; it has a single entry,
+ * is non-auto-refill (some other way(s) must be auto-refill),
+ * all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ * restriction is that this be the only page size it supports).
+ *
+ * TLB way entries are virtually indexed.
+ * TLB ways that support multiple page sizes:
+ * - must have all writable VPN and PPN fields;
+ * - can only use one page size at any given time (eg. setup at startup),
+ * selected by the respective ITLBCFG or DTLBCFG special register,
+ * whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ * this list may be sparse for auto-refill ways because auto-refill
+ * ways have independent lists of supported page sizes sharing a
+ * common encoding with PTE entries; the encoding is the index into
+ * this list; unsupported sizes for a given way are zero in the list;
+ * selecting unsupported sizes results in undefined hardware behaviour;
+ * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
***************
*** 819,836 ****
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
! #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure */
! #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure */
- /* Instruction TLB: */
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
! #define XCHAL_ITLB_WAYS 7 /* number of ways */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
- /* Data TLB: */
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
! #define XCHAL_DTLB_WAYS 10 /* number of ways */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
- /* ... */
/*
--- 705,1022 ----
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
! #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
! #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
!
!
! /*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
! #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
+ #define XCHAL_ITLB_SETS 4 /* number of sets (groups of ways with identical settings) */
+
+ /* Way set to which each way belongs: */
+ #define XCHAL_ITLB_WAY0_SET 0
+ #define XCHAL_ITLB_WAY1_SET 0
+ #define XCHAL_ITLB_WAY2_SET 0
+ #define XCHAL_ITLB_WAY3_SET 0
+ #define XCHAL_ITLB_WAY4_SET 1
+ #define XCHAL_ITLB_WAY5_SET 2
+ #define XCHAL_ITLB_WAY6_SET 3
+
+ /* Ways sets that are used by hardware auto-refill (ARF): */
+ #define XCHAL_ITLB_ARF_SETS 1 /* number of auto-refill sets */
+ #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
+
+ /* Way sets that are "min-wired" (see terminology comment above): */
+ #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
+
+
+ /* ITLB way set 0 (group of ways 0 thru 3): */
+ #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* ITLB way set 1 (group of ways 4 thru 4): */
+ #define XCHAL_ITLB_SET1_WAY 4 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* ITLB way set 2 (group of ways 5 thru 5): */
+ #define XCHAL_ITLB_SET2_WAY 5 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_ASID_CONST 0x01
+ #define XCHAL_ITLB_SET2_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_VPN_CONST 0xD0000000
+ #define XCHAL_ITLB_SET2_E1_VPN_CONST 0xD8000000
+ /* Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_PPN_CONST 0x00000000
+ #define XCHAL_ITLB_SET2_E1_PPN_CONST 0x00000000
+ /* Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_CA_CONST 0x07
+ #define XCHAL_ITLB_SET2_E1_CA_CONST 0x03
+
+ /* ITLB way set 3 (group of ways 6 thru 6): */
+ #define XCHAL_ITLB_SET3_WAY 6 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_ASID_CONST 0x01
+ #define XCHAL_ITLB_SET3_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_VPN_CONST 0xE0000000
+ #define XCHAL_ITLB_SET3_E1_VPN_CONST 0xF0000000
+ /* Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_PPN_CONST 0xF0000000
+ #define XCHAL_ITLB_SET3_E1_PPN_CONST 0xF0000000
+ /* Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_CA_CONST 0x07
+ #define XCHAL_ITLB_SET3_E1_CA_CONST 0x03
+
+ /* Indexing macros: */
+ #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
+ #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
+ #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
+ #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
+ /*
+ * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+
+ /*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
! #define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
+ #define XCHAL_DTLB_SETS 5 /* number of sets (groups of ways with identical settings) */
+
+ /* Way set to which each way belongs: */
+ #define XCHAL_DTLB_WAY0_SET 0
+ #define XCHAL_DTLB_WAY1_SET 0
+ #define XCHAL_DTLB_WAY2_SET 0
+ #define XCHAL_DTLB_WAY3_SET 0
+ #define XCHAL_DTLB_WAY4_SET 1
+ #define XCHAL_DTLB_WAY5_SET 2
+ #define XCHAL_DTLB_WAY6_SET 3
+ #define XCHAL_DTLB_WAY7_SET 4
+ #define XCHAL_DTLB_WAY8_SET 4
+ #define XCHAL_DTLB_WAY9_SET 4
+
+ /* Ways sets that are used by hardware auto-refill (ARF): */
+ #define XCHAL_DTLB_ARF_SETS 1 /* number of auto-refill sets */
+ #define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
+
+ /* Way sets that are "min-wired" (see terminology comment above): */
+ #define XCHAL_DTLB_MINWIRED_SETS 1 /* number of "min-wired" sets */
+ #define XCHAL_DTLB_MINWIRED_SET0 4 /* index of n'th "min-wired" set */
+
+
+ /* DTLB way set 0 (group of ways 0 thru 3): */
+ #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* DTLB way set 1 (group of ways 4 thru 4): */
+ #define XCHAL_DTLB_SET1_WAY 4 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* DTLB way set 2 (group of ways 5 thru 5): */
+ #define XCHAL_DTLB_SET2_WAY 5 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_ASID_CONST 0x01
+ #define XCHAL_DTLB_SET2_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_VPN_CONST 0xD0000000
+ #define XCHAL_DTLB_SET2_E1_VPN_CONST 0xD8000000
+ /* Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_PPN_CONST 0x00000000
+ #define XCHAL_DTLB_SET2_E1_PPN_CONST 0x00000000
+ /* Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_CA_CONST 0x07
+ #define XCHAL_DTLB_SET2_E1_CA_CONST 0x03
+
+ /* DTLB way set 3 (group of ways 6 thru 6): */
+ #define XCHAL_DTLB_SET3_WAY 6 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_ASID_CONST 0x01
+ #define XCHAL_DTLB_SET3_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_VPN_CONST 0xE0000000
+ #define XCHAL_DTLB_SET3_E1_VPN_CONST 0xF0000000
+ /* Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_PPN_CONST 0xF0000000
+ #define XCHAL_DTLB_SET3_E1_PPN_CONST 0xF0000000
+ /* Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_CA_CONST 0x07
+ #define XCHAL_DTLB_SET3_E1_CA_CONST 0x03
+
+ /* DTLB way set 4 (group of ways 7 thru 9): */
+ #define XCHAL_DTLB_SET4_WAY 7 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET4_WAYS 3 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET4_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET4_ENTRIES 1 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET4_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET4_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* Indexing macros: */
+ #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
+ #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
+ #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
+ #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
+ /*
+ * Example use: XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
/*
***************
*** 877,885 ****
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00006700 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
! #define XCHAL_HW_CONFIGID0 0xC10FD3FF /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00806700 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
--- 1063,1071 ----
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
! #define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
***************
*** 1001,1008 ****
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
- #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
! #define XCHAL_HAVE_NSA 1 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
--- 1187,1193 ----
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
! #define XCHAL_HAVE_NSA 0 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
***************
*** 1010,1024 ****
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
- #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
- #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
- #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
! #define XCHAL_HAVE_PRID 1 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
--- 1195,1212 ----
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
! #define XCHAL_HAVE_PRID 0 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
+
+ /* These relate a bit more to TIE: */
+ #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
+ #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
Index: defs.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/defs.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** defs.h 23 Oct 2002 20:53:21 -0000 1.1
--- defs.h 7 Mar 2003 19:15:17 -0000 1.2
***************
*** 1,18 ****
! #ifndef _XTENSA_BASE_HEADER
! #define _XTENSA_BASE_HEADER
/*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/defs.h -- Definitions for Xtensa
! * instructions, types, and protos.
! *
! * This file is subject to the terms and conditions of the GNU General Public
! * License. See the file "COPYING" in the main directory of this archive
! * for more details.
! *
! * Copyright (C) 2002 Tensilica Inc.
*/
#ifdef __XTENSA__
--- 1,32 ----
! /* Definitions for Xtensa instructions, types, and protos. */
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
+ /* Do not modify. This is automatically generated.*/
+
+ #ifndef _XTENSA_BASE_HEADER
+ #define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
***************
*** 206,234 ****
- #define NSA_ASM(arr, ars) {\
- __asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
- }
-
- #define XT_NSA(ars) \
- ({ \
- unsigned _arr; \
- int _ars = ars; \
- NSA_ASM(_arr, _ars); \
- _arr; \
- })
-
- #define NSAU_ASM(arr, ars) {\
- __asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
- }
-
- #define XT_NSAU(ars) \
- ({ \
- unsigned _arr; \
- unsigned _ars = ars; \
- NSAU_ASM(_arr, _ars); \
- _arr; \
- })
-
-
#endif /* __GNUC__ && !__XCC__ */
--- 220,223 ----
***************
*** 275,283 ****
#define XT_SSAI _TIE_SSAI
- /* Miscellaneous instructions */
- extern unsigned _TIE_NSA(int ars);
- extern unsigned _TIE_NSAU(unsigned ars);
- #define XT_NSA _TIE_NSA
- #define XT_NSAU _TIE_NSAU
#endif /* __XCC__ */
--- 264,267 ----
Index: specreg.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/specreg.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** specreg.h 23 Oct 2002 20:53:21 -0000 1.1
--- specreg.h 7 Mar 2003 19:15:18 -0000 1.2
***************
*** 1,18 ****
! #ifndef XTENSA_SPECREG_H
! #define XTENSA_SPECREG_H
/*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/specreg.h
! * Xtensa Special Register symbolic names.
! *
! * This file is subject to the terms and conditions of the GNU General Public
! * License. See the file "COPYING" in the main directory of this archive
! * for more details.
! *
! * Copyright (C) 2002 Tensilica Inc.
*/
/* Include these special register bitfield definitions, for historical reasons: */
--- 1,34 ----
! /*
! * Xtensa Special Register symbolic names
! */
!
! /* $Id$ */
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
+ #ifndef XTENSA_SPECREG_H
+ #define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
***************
*** 57,61 ****
#define DEBUGCAUSE 233
#define CCOUNT 234
- #define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
--- 73,76 ----
Index: system.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/system.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** system.h 23 Oct 2002 20:53:21 -0000 1.1
--- system.h 7 Mar 2003 19:15:18 -0000 1.2
***************
*** 1,25 ****
! #ifndef XTENSA_CONFIG_SYSTEM_H
! #define XTENSA_CONFIG_SYSTEM_H
/*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/system.h -- HAL definitions that
! * are dependent on SYSTEM configuration.
*
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * The HAL itself has historically included this file in some
! * instances, but this is not appropriate either because the HAL is
! * meant to be core-specific but system independent.
! *
! * This file is subject to the terms and conditions of the GNU General
! * Public License. See the file "COPYING" in the main directory of
! * this archive for more details.
! *
! * Copyright (C) 2002 Tensilica Inc.
*/
/*#include <xtensa/hal.h>*/
--- 1,42 ----
! /*
! * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
! *
! * NOTE: The location and contents of this file are highly subject to change.
! *
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * The HAL itself has historically included this file in some instances,
! * but this is not appropriate either, because the HAL is meant to be
! * core-specific but system independent.
! */
/*
! * C...
[truncated message content] |
|
From: <joe...@us...> - 2003-03-07 19:15:32
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test
In directory sc8-pr-cvs1:/tmp/cvs-serv31823/include/asm-xtensa/xtensa/config-linux_test
Modified Files:
core.h defs.h specreg.h system.h
Added Files:
tie.h
Log Message:
Update config-specific files with later versions. Removes the NSA/NSAU option from the baseline configs, corrects copyright info, and adds more macros to improve kernel implementation.
--- NEW FILE: tie.h ---
/*
* xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration,
* and furthermore for a specific set of TIE source files that extend
* basic core functionality.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_CONFIG_TIE_H
#define XTENSA_CONFIG_TIE_H
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_CP_NUM 4 /* number of coprocessors */
#define XCHAL_CP_MAX 7 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MASK 0x65 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 72
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 68
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 136
#define XCHAL_CP6_SA_SIZE 36
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 4
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 4
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 8
#define XCHAL_CP6_SA_ALIGN 4
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 28
#define XCHAL_EXTRA_SA_ALIGN 4
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 340 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 8
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
// Start saving state for MAC16
rsr a3, ACCLO
s32i a3, a2, 0
rsr a3, ACCHI
s32i a3, a2, 4
rsr a3, MR_0
s32i a3, a2, 8
rsr a3, MR_1
s32i a3, a2, 12
rsr a3, MR_2
s32i a3, a2, 16
rsr a3, MR_3
s32i a3, a2, 20
// End of saving state for MAC16
// Start saving state for Booleans
rsr a3, BR
s32i a3, a2, 24
// End of saving state for Booleans
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
// begin restore state for MAC16
l32i a3, a2, 0
wsr a3, ACCLO
l32i a3, a2, 4
wsr a3, ACCHI
l32i a3, a2, 8
wsr a3, MR_0
l32i a3, a2, 12
wsr a3, MR_1
l32i a3, a2, 16
wsr a3, MR_2
l32i a3, a2, 20
wsr a3, MR_3
// end restore state for MAC16
// begin restore state for Booleans
l32i a3, a2, 24
wsr a3, BR
// end restore state for Booleans
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
#define xchal_cp_cp0_store xchal_cp0_store
#define xchal_cp_cp0_store_a2 xchal_cp0_store_a2
#define xchal_cp0_store_a2 xchal_cp0_store a2, a3
// Name: xchal_cp0_store
// This macro saves the states of cp0
// Prototype: xchal_cp0_store a_0 a_1
// Pointer to memory: a_0, aligned to 4 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp0_store a_0 a_1
rur232 \a_1
s32i \a_1, \a_0, 0
rur233 \a_1
s32i \a_1, \a_0, 4
addi \a_0, \a_0, 8
ssi f0, \a_0, 0
ssi f1, \a_0, 4
ssi f2, \a_0, 8
ssi f3, \a_0, 12
ssi f4, \a_0, 16
ssi f5, \a_0, 20
ssi f6, \a_0, 24
ssi f7, \a_0, 28
ssi f8, \a_0, 32
ssi f9, \a_0, 36
ssi f10, \a_0, 40
ssi f11, \a_0, 44
ssi f12, \a_0, 48
ssi f13, \a_0, 52
ssi f14, \a_0, 56
ssi f15, \a_0, 60
.endm // xchal_cp0_store
#define xchal_cp_cp0_load xchal_cp0_load
#define xchal_cp_cp0_load_a2 xchal_cp0_load_a2
#define xchal_cp0_load_a2 xchal_cp0_load a2, a3
// Name: xchal_cp0_load
// This macro restores the states of cp0
// Prototype: xchal_cp0_load a_0 a_1
// Pointer to memory: a_0, aligned to 4 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp0_load a_0 a_1
l32i \a_1, \a_0, 0
wur232 \a_1
l32i \a_1, \a_0, 4
wur233 \a_1
addi \a_0, \a_0, 8
lsi f0, \a_0, 0
lsi f1, \a_0, 4
lsi f2, \a_0, 8
lsi f3, \a_0, 12
lsi f4, \a_0, 16
lsi f5, \a_0, 20
lsi f6, \a_0, 24
lsi f7, \a_0, 28
lsi f8, \a_0, 32
lsi f9, \a_0, 36
lsi f10, \a_0, 40
lsi f11, \a_0, 44
lsi f12, \a_0, 48
lsi f13, \a_0, 52
lsi f14, \a_0, 56
lsi f15, \a_0, 60
.endm // xchal_cp0_load
#define xchal_cp_cp6_store xchal_cp6_store
#define xchal_cp_cp6_store_a2 xchal_cp6_store_a2
#define xchal_cp6_store_a2 xchal_cp6_store a2, a3
// Name: xchal_cp6_store
// This macro saves the states of cp6
// Prototype: xchal_cp6_store a_0 a_1
// Pointer to memory: a_0, aligned to 4 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp6_store a_0 a_1
rur0 \a_1
s32i \a_1, \a_0, 0
addi \a_0, \a_0, 4
i16_si i160, \a_0, 0
i16_si i161, \a_0, 2
i16_si i162, \a_0, 4
i16_si i163, \a_0, 6
i16_si i164, \a_0, 8
i16_si i165, \a_0, 10
i16_si i166, \a_0, 12
i16_si i167, \a_0, 14
i16_si i168, \a_0, 16
i16_si i169, \a_0, 18
i16_si i1610, \a_0, 20
i16_si i1611, \a_0, 22
i16_si i1612, \a_0, 24
i16_si i1613, \a_0, 26
i16_si i1614, \a_0, 28
i16_si i1615, \a_0, 30
.endm // xchal_cp6_store
#define xchal_cp_cp6_load xchal_cp6_load
#define xchal_cp_cp6_load_a2 xchal_cp6_load_a2
#define xchal_cp6_load_a2 xchal_cp6_load a2, a3, a4, a5
// Name: xchal_cp6_load
// This macro restores the states of cp6
// Prototype: xchal_cp6_load a_0 a_1 a_2 a_3
// Pointer to memory: a_0, aligned to 4 bytes
// Scratch register needed: a_1 a_2 a_3
// Example use:
//
// Clobbers:
// a_0 a_1 a_2 a_3
.macro xchal_cp6_load a_0 a_1 a_2 a_3
l32i \a_1, \a_0, 0
rur0 \a_2
movi \a_3, 0x0000ffff
xor \a_1, \a_1, \a_2
and \a_1, \a_1, \a_3
xor \a_1, \a_1, \a_2
wur0 \a_1
addi \a_0, \a_0, 4
i16_li i160, \a_0, 0
i16_li i161, \a_0, 2
i16_li i162, \a_0, 4
i16_li i163, \a_0, 6
i16_li i164, \a_0, 8
i16_li i165, \a_0, 10
i16_li i166, \a_0, 12
i16_li i167, \a_0, 14
i16_li i168, \a_0, 16
i16_li i169, \a_0, 18
i16_li i1610, \a_0, 20
i16_li i1611, \a_0, 22
i16_li i1612, \a_0, 24
i16_li i1613, \a_0, 26
i16_li i1614, \a_0, 28
i16_li i1615, \a_0, 30
.endm // xchal_cp6_load
#define xchal_cp_cp2_store xchal_cp2_store
#define xchal_cp_cp2_store_a2 xchal_cp2_store_a2
#define xchal_cp2_store_a2 xchal_cp2_store a2, a3
// Name: xchal_cp2_store
// This macro saves the states of cp2
// Prototype: xchal_cp2_store a_0 a_1
// Pointer to memory: a_0, aligned to 4 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp2_store a_0 a_1
rur1 \a_1
s32i \a_1, \a_0, 0
addi \a_0, \a_0, 4
i32_si i320, \a_0, 0
i32_si i321, \a_0, 4
i32_si i322, \a_0, 8
i32_si i323, \a_0, 12
i32_si i324, \a_0, 16
i32_si i325, \a_0, 20
i32_si i326, \a_0, 24
i32_si i327, \a_0, 28
i32_si i328, \a_0, 32
i32_si i329, \a_0, 36
i32_si i3210, \a_0, 40
i32_si i3211, \a_0, 44
i32_si i3212, \a_0, 48
i32_si i3213, \a_0, 52
i32_si i3214, \a_0, 56
i32_si i3215, \a_0, 60
.endm // xchal_cp2_store
#define xchal_cp_cp2_load xchal_cp2_load
#define xchal_cp_cp2_load_a2 xchal_cp2_load_a2
#define xchal_cp2_load_a2 xchal_cp2_load a2, a3
// Name: xchal_cp2_load
// This macro restores the states of cp2
// Prototype: xchal_cp2_load a_0 a_1
// Pointer to memory: a_0, aligned to 4 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp2_load a_0 a_1
l32i \a_1, \a_0, 0
wur1 \a_1
addi \a_0, \a_0, 4
i32_li i320, \a_0, 0
i32_li i321, \a_0, 4
i32_li i322, \a_0, 8
i32_li i323, \a_0, 12
i32_li i324, \a_0, 16
i32_li i325, \a_0, 20
i32_li i326, \a_0, 24
i32_li i327, \a_0, 28
i32_li i328, \a_0, 32
i32_li i329, \a_0, 36
i32_li i3210, \a_0, 40
i32_li i3211, \a_0, 44
i32_li i3212, \a_0, 48
i32_li i3213, \a_0, 52
i32_li i3214, \a_0, 56
i32_li i3215, \a_0, 60
.endm // xchal_cp2_load
#define xchal_cp_cp5_store xchal_cp5_store
#define xchal_cp_cp5_store_a2 xchal_cp5_store_a2
#define xchal_cp5_store_a2 xchal_cp5_store a2, a3
// Name: xchal_cp5_store
// This macro saves the states of cp5
// Prototype: xchal_cp5_store a_0 a_1
// Pointer to memory: a_0, aligned to 8 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp5_store a_0 a_1
rur2 \a_1
s32i \a_1, \a_0, 0
rur3 \a_1
s32i \a_1, \a_0, 4
addi \a_0, \a_0, 8
i64_si i640, \a_0, 0
i64_si i641, \a_0, 8
i64_si i642, \a_0, 16
i64_si i643, \a_0, 24
i64_si i644, \a_0, 32
i64_si i645, \a_0, 40
i64_si i646, \a_0, 48
i64_si i647, \a_0, 56
i64_si i648, \a_0, 64
i64_si i649, \a_0, 72
i64_si i6410, \a_0, 80
i64_si i6411, \a_0, 88
i64_si i6412, \a_0, 96
i64_si i6413, \a_0, 104
i64_si i6414, \a_0, 112
i64_si i6415, \a_0, 120
.endm // xchal_cp5_store
#define xchal_cp_cp5_load xchal_cp5_load
#define xchal_cp_cp5_load_a2 xchal_cp5_load_a2
#define xchal_cp5_load_a2 xchal_cp5_load a2, a3
// Name: xchal_cp5_load
// This macro restores the states of cp5
// Prototype: xchal_cp5_load a_0 a_1
// Pointer to memory: a_0, aligned to 8 bytes
// Scratch register needed: a_1
// Example use:
//
// Clobbers:
// a_0 a_1
.macro xchal_cp5_load a_0 a_1
l32i \a_1, \a_0, 0
wur2 \a_1
l32i \a_1, \a_0, 4
wur3 \a_1
addi \a_0, \a_0, 8
i64_li i640, \a_0, 0
i64_li i641, \a_0, 8
i64_li i642, \a_0, 16
i64_li i643, \a_0, 24
i64_li i644, \a_0, 32
i64_li i645, \a_0, 40
i64_li i646, \a_0, 48
i64_li i647, \a_0, 56
i64_li i648, \a_0, 64
i64_li i649, \a_0, 72
i64_li i6410, \a_0, 80
i64_li i6411, \a_0, 88
i64_li i6412, \a_0, 96
i64_li i6413, \a_0, 104
i64_li i6414, \a_0, 112
i64_li i6415, \a_0, 120
.endm // xchal_cp5_load
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
bnez a3, 99f
xchal_cp_cp0_store_a2
j .Lcpi_store_end_\@
99:
bnei a3, 6, 99f
xchal_cp_cp6_store_a2
j .Lcpi_store_end_\@
99:
bnei a3, 2, 99f
xchal_cp_cp2_store_a2
j .Lcpi_store_end_\@
99:
bnei a3, 5, 99f
xchal_cp_cp5_store_a2
j .Lcpi_store_end_\@
99:
.Lcpi_store_end_\@:
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
bnez a3, 99f
xchal_cp_cp0_load_a2
j .Lcpi_load_end_\@
99:
bnei a3, 6, 99f
xchal_cp_cp6_load_a2
j .Lcpi_load_end_\@
99:
bnei a3, 2, 99f
xchal_cp_cp2_load_a2
j .Lcpi_load_end_\@
99:
bnei a3, 5, 99f
xchal_cp_cp5_load_a2
j .Lcpi_load_end_\@
99:
.Lcpi_load_end_\@:
.endm
#endif /*_ASMLANGUAGE*/
/*
* Contents of save areas in terms of libdb register numbers.
* NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
* it is up to the user of this header file to define these macros
* usefully before each expansion of the CONTENTS_LIBDB macros.
* (Fields rsv[123] are reserved for future additions; they are currently
* set to zero but may be set to some useful values in the future.)
*
* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
*/
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 7
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB \
CONTENTS_LIBDB_SREG(0x08000010, 0, 4, 4, 0, "ACCLO", 16, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_SREG(0x08000011, 4, 4, 4, 0, "ACCHI", 17, 0x000000FF, 0,0) \
CONTENTS_LIBDB_SREG(0x08000020, 8, 4, 4, 0, "MR0", 32, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_SREG(0x08000021, 12, 4, 4, 0, "MR1", 33, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_SREG(0x08000022, 16, 4, 4, 0, "MR2", 34, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_SREG(0x08000023, 20, 4, 4, 0, "MR3", 35, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_SREG(0x08000004, 24, 4, 4, 0, "BR", 4, 0x0000FFFF, 0,0) \
/* end */
#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 18
#define XCHAL_CP0_SA_CONTENTS_LIBDB \
CONTENTS_LIBDB_UREG(0x0C0000E8, 0, 4, 4, 0, "FCR", 232, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_UREG(0x0C0000E9, 4, 4, 4, 0, "FSR", 233, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_REGF(0x10030000, 8, 4, 4, 0, "f0", 0, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030001, 12, 4, 4, 0, "f1", 1, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030002, 16, 4, 4, 0, "f2", 2, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030003, 20, 4, 4, 0, "f3", 3, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030004, 24, 4, 4, 0, "f4", 4, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030005, 28, 4, 4, 0, "f5", 5, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030006, 32, 4, 4, 0, "f6", 6, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030007, 36, 4, 4, 0, "f7", 7, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030008, 40, 4, 4, 0, "f8", 8, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x10030009, 44, 4, 4, 0, "f9", 9, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x1003000A, 48, 4, 4, 0, "f10", 10, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x1003000B, 52, 4, 4, 0, "f11", 11, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x1003000C, 56, 4, 4, 0, "f12", 12, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x1003000D, 60, 4, 4, 0, "f13", 13, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x1003000E, 64, 4, 4, 0, "f14", 14, 16, 4, "f", "FR", 0,0) \
CONTENTS_LIBDB_REGF(0x1003000F, 68, 4, 4, 0, "f15", 15, 16, 4, "f", "FR", 0,0) \
/* end */
#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 17
#define XCHAL_CP2_SA_CONTENTS_LIBDB \
CONTENTS_LIBDB_UREG(0x0C000001, 0, 4, 4, 0, "UR1", 1, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_REGF(0x10050000, 4, 4, 4, 0, "i320", 0, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050001, 8, 4, 4, 0, "i321", 1, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050002, 12, 4, 4, 0, "i322", 2, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050003, 16, 4, 4, 0, "i323", 3, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050004, 20, 4, 4, 0, "i324", 4, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050005, 24, 4, 4, 0, "i325", 5, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050006, 28, 4, 4, 0, "i326", 6, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050007, 32, 4, 4, 0, "i327", 7, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050008, 36, 4, 4, 0, "i328", 8, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x10050009, 40, 4, 4, 0, "i329", 9, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x1005000A, 44, 4, 4, 0, "i3210", 10, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x1005000B, 48, 4, 4, 0, "i3211", 11, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x1005000C, 52, 4, 4, 0, "i3212", 12, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x1005000D, 56, 4, 4, 0, "i3213", 13, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x1005000E, 60, 4, 4, 0, "i3214", 14, 16, 4, "i32", "i32", 0,0) \
CONTENTS_LIBDB_REGF(0x1005000F, 64, 4, 4, 0, "i3215", 15, 16, 4, "i32", "i32", 0,0) \
/* end */
#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 18
#define XCHAL_CP5_SA_CONTENTS_LIBDB \
CONTENTS_LIBDB_UREG(0x0C000002, 0, 4, 4, 0, "S64HI", 2, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_UREG(0x0C000003, 4, 4, 4, 0, "S64LO", 3, 0xFFFFFFFF, 0,0) \
CONTENTS_LIBDB_REGF(0x10040000, 8, 8, 8, 0, "i640", 0, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040001, 16, 8, 8, 0, "i641", 1, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040002, 24, 8, 8, 0, "i642", 2, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040003, 32, 8, 8, 0, "i643", 3, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040004, 40, 8, 8, 0, "i644", 4, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040005, 48, 8, 8, 0, "i645", 5, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040006, 56, 8, 8, 0, "i646", 6, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040007, 64, 8, 8, 0, "i647", 7, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040008, 72, 8, 8, 0, "i648", 8, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x10040009, 80, 8, 8, 0, "i649", 9, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x1004000A, 88, 8, 8, 0, "i6410", 10, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x1004000B, 96, 8, 8, 0, "i6411", 11, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x1004000C, 104, 8, 8, 0, "i6412", 12, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x1004000D, 112, 8, 8, 0, "i6413", 13, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x1004000E, 120, 8, 8, 0, "i6414", 14, 16, 8, "i64", "i64", 0,0) \
CONTENTS_LIBDB_REGF(0x1004000F, 128, 8, 8, 0, "i6415", 15, 16, 8, "i64", "i64", 0,0) \
/* end */
#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 17
#define XCHAL_CP6_SA_CONTENTS_LIBDB \
CONTENTS_LIBDB_UREG(0x0C000000, 0, 4, 4, 0, "UR0", 0, 0x0000FFFF, 0,0) \
CONTENTS_LIBDB_REGF(0x10060000, 4, 2, 2, 0, "i160", 0, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060001, 6, 2, 2, 0, "i161", 1, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060002, 8, 2, 2, 0, "i162", 2, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060003, 10, 2, 2, 0, "i163", 3, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060004, 12, 2, 2, 0, "i164", 4, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060005, 14, 2, 2, 0, "i165", 5, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060006, 16, 2, 2, 0, "i166", 6, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060007, 18, 2, 2, 0, "i167", 7, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060008, 20, 2, 2, 0, "i168", 8, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x10060009, 22, 2, 2, 0, "i169", 9, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x1006000A, 24, 2, 2, 0, "i1610", 10, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x1006000B, 26, 2, 2, 0, "i1611", 11, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x1006000C, 28, 2, 2, 0, "i1612", 12, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x1006000D, 30, 2, 2, 0, "i1613", 13, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x1006000E, 32, 2, 2, 0, "i1614", 14, 16, 2, "i16", "i16", 0,0) \
CONTENTS_LIBDB_REGF(0x1006000F, 34, 2, 2, 0, "i1615", 15, 16, 2, "i16", "i16", 0,0) \
/* end */
#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#if 0 /* is there something equivalent for user TIE? */
#define XCHAL_CORE_ID "linux_test" /* configuration's alphanumeric core identifier
(CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x000063EB /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC1FFDFFE /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x008063EB /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
#endif /*0*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
#define XCHAL_HAVE_BOOLEANS 1 /* 1 if booleans option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
#define XCHAL_HAVE_FP 1 /* 1 if floating point option configured, 0 otherwise */
#endif /*0*/
#endif /*XTENSA_CONFIG_TIE_H*/
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/core.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** core.h 7 Feb 2003 02:03:35 -0000 1.5
--- core.h 7 Mar 2003 19:15:22 -0000 1.6
***************
*** 11,20 ****
/*
! * Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
[...1137 lines suppressed...]
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
- #define XCHAL_HAVE_FP 1 /* 1 if floating point option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
--- 1275,1281 ----
***************
*** 1500,1503 ****
--- 1283,1292 ----
#define XCHAL_NUM_MISC_REGS 4 /* number of miscellaneous registers (0..4) */
+
+ /* These relate a bit more to TIE: */
+ #define XCHAL_HAVE_BOOLEANS 1 /* 1 if booleans option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
+ #define XCHAL_HAVE_FP 1 /* 1 if floating point option configured, 0 otherwise */
Index: defs.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/defs.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** defs.h 17 Jan 2003 18:17:49 -0000 1.2
--- defs.h 7 Mar 2003 19:15:23 -0000 1.3
***************
*** 2,11 ****
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 2,26 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
Index: specreg.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/specreg.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** specreg.h 17 Jan 2003 18:17:50 -0000 1.2
--- specreg.h 7 Mar 2003 19:15:23 -0000 1.3
***************
*** 6,15 ****
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 6,30 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
Index: system.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/system.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** system.h 17 Jan 2003 18:17:50 -0000 1.2
--- system.h 7 Mar 2003 19:15:23 -0000 1.3
***************
*** 12,21 ****
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
! * These coded instructions, statements, and computer programs are the
! * copyrighted works and confidential proprietary information of Tensilica Inc.
! * They may not be modified, copied, reproduced, distributed, or disclosed to
! * third parties in any manner, medium, or form, in whole or in part, without
! * the prior written consent of Tensilica Inc.
*/
--- 12,36 ----
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
***************
*** 48,63 ****
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
- #if 0
- #define XSHAL_ETHER_VADDR 0xFD030000
- #define XSHAL_ETHER_PADDR 0xFD030000
- #define XSHAL_UART_VADDR 0xFD050000
- #define XSHAL_UART_PADDR 0xFD050000
- #define XSHAL_LED_VADDR 0xFD040000
- #define XSHAL_LED_PADDR 0xFD040000
- #define XSHAL_FLASH_VADDR 0xF8000000
- #define XSHAL_FLASH_PADDR 0xF8000000
- #define XSHAL_FLASH_SIZE 0x04000000
- #endif /*0*/
-
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
--- 63,66 ----
***************
*** 113,118 ****
* particular target environments' memory maps.
*/
! #define XSHAL_CACHEATTR_BYPASS 0x22FFFFF2 /* disable caches in bypass mode */
! #define XSHAL_CACHEATTR_DEFAULT 0x22FFFFF1 /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
--- 116,121 ----
* particular target environments' memory maps.
*/
! #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
! #define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
***************
*** 125,128 ****
--- 128,142 ----
#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
+
+ /* For Coware only: */
+ #define XSHAL_COWARE_CACHEATTR_WRITEBACK 0x44222222 /* enable caches in write-back mode */
+ #define XSHAL_COWARE_CACHEATTR_WRITEALLOC 0x11222222 /* enable caches in write-allocate mode */
+ #define XSHAL_COWARE_CACHEATTR_WRITETHRU 0x11222222 /* enable caches in write-through mode */
+ #define XSHAL_COWARE_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
+ #define XSHAL_COWARE_CACHEATTR_DEFAULT XSHAL_COWARE_CACHEATTR_WRITEBACK /* default setting to enable caches */
+
+ /* For BFM and other purposes: */
+ #define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x44222222 /* enable caches without any invalid regions */
+ #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting for caches without any invalid regions */
#define XSHAL_ISS_PIPE_REGIONS 0
|
|
From: <jn...@us...> - 2003-03-05 17:57:53
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv32016/include/asm-xtensa
Modified Files:
pgtable.h
Log Message:
Fixed two fundamental problems with writeback cache plus cache
aliasing.
1) set_pte -- When writing to a pte, that pte may be mapped into the
pagetable, and it may be aliased. It's important that the
pte when written be flushed back to memory so that when the
autorefill happens, it will read the fresh copy.
It would probably be more efficient to allocate these pages of
ptes as writethru instead of writing back the line everytime
set_pte happens.
2) copy_user_page -- There are facilities to make the to and address parameters
unaliased, but there isn't for the from address. So it seems that
there is the chance that any writes that happened to the from page,
may be in a different cache line. It seems necessart to force the
data cache to be written back at this point.
Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** pgtable.h 28 Feb 2003 01:53:10 -0000 1.8
--- pgtable.h 5 Mar 2003 17:57:46 -0000 1.9
***************
*** 345,348 ****
--- 345,356 ----
{
*ptep = pteval;
+ #if (XCHAL_DCACHE_IS_WRITEBACK > 0) && (XTENSA_CACHE_ALIAS > 0)
+ {
+ unsigned long flags;
+ save_and_cli(flags);
+ xthal_dcache_line_writeback((void*)ptep);
+ restore_flags(flags);
+ }
+ #endif
}
|
|
From: <jn...@us...> - 2003-03-05 17:57:53
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv32016/arch/xtensa/mm
Modified Files:
cache.c fault.c mmu.c
Log Message:
Fixed two fundamental problems with writeback cache plus cache
aliasing.
1) set_pte -- When writing to a pte, that pte may be mapped into the
pagetable, and it may be aliased. It's important that the
pte when written be flushed back to memory so that when the
autorefill happens, it will read the fresh copy.
It would probably be more efficient to allocate these pages of
ptes as writethru instead of writing back the line everytime
set_pte happens.
2) copy_user_page -- There are facilities to make the to and address parameters
unaliased, but there isn't for the from address. So it seems that
there is the chance that any writes that happened to the from page,
may be in a different cache line. It seems necessart to force the
data cache to be written back at this point.
Index: cache.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/cache.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** cache.c 28 Feb 2003 23:18:49 -0000 1.7
--- cache.c 5 Mar 2003 17:57:44 -0000 1.8
***************
*** 180,186 ****
-
-
-
/* 20feb2003 -- jn
* some subset of these functions need to be available when
--- 180,183 ----
***************
*** 194,199 ****
--- 191,198 ----
unsigned long addr = (unsigned long) page_address(page);
unsigned long flags;
+
save_and_cli(flags);
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
+ xthal_icache_region_invalidate((void*)addr, PAGE_SIZE);
restore_flags(flags);
}
***************
*** 204,207 ****
--- 203,207 ----
{
unsigned long flags;
+
save_and_cli(flags);
#if defined(XCHAL_DCACHE_IS_WRITEBACK)
***************
*** 252,257 ****
unsigned long addr = (unsigned long) page_address(page);
unsigned long flags;
save_and_cli(flags);
! #if 1
#if defined(XCHAL_DCACHE_IS_WRITEBACK)
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
--- 252,258 ----
unsigned long addr = (unsigned long) page_address(page);
unsigned long flags;
+
save_and_cli(flags);
! #if 0
#if defined(XCHAL_DCACHE_IS_WRITEBACK)
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
***************
*** 262,268 ****
/* XTFIXME -- this is just a test, going to flush the entire cache
* cache and see if that makes it start working.
! */
// printk("flush_dcache_page: addr=0x%08x\n", addr);
! xthal_dcache_all_writeback_inv();
#endif
--- 263,270 ----
/* XTFIXME -- this is just a test, going to flush the entire cache
* cache and see if that makes it start working.
! */
// printk("flush_dcache_page: addr=0x%08x\n", addr);
! flush_cache_all();
! // xthal_dcache_all_writeback_inv();
#endif
***************
*** 274,277 ****
--- 276,298 ----
void clear_user_page(void *to, unsigned long address)
{
+ #if XCHAL_DCACHE_IS_WRITEBACK
+ unsigned long flags;
+
+ /* 03mar2003 jn
+ * I had a dream last night.... And in that dream I saw
+ * a process being copied... But the the page "from" which
+ * that process was being copied was an alias to the physical
+ * page. And with cache aliasing, the data that was being
+ * read was not in sync...
+ * Therefore, at this point, we need to flush the writeback
+ * cache before we do the copy.
+ */
+
+ save_and_cli(flags);
+ xthal_dcache_all_writeback();
+ restore_flags(flags);
+
+ #endif
+
if ( (( (unsigned long)to ^ address) & XT_CACHE_ALIAS_BITS) == 0) {
clear_page(to);
***************
*** 282,285 ****
--- 303,309 ----
unsigned long vpnval;
pte_t pteval;
+ #if XCHAL_DCACHE_IS_WRITEBACK
+ unsigned long flags;
+ #endif
new_to = new_to + (address & XT_CACHE_ALIAS_BITS);
***************
*** 289,292 ****
--- 313,327 ----
write_dtlb_entry(pteval, vpnval);
clear_page((void *)new_to);
+
+ /* XTFIXME -- would it be better to allocate the
+ * new_to pte as writethru, instead of
+ * having to writeback the cache at this
+ * point?
+ */
+ #if XCHAL_DCACHE_IS_WRITEBACK
+ save_and_cli(flags);
+ xthal_dcache_all_writeback();
+ restore_flags(flags);
+ #endif
up(&dealias_page_sem);
}
***************
*** 301,305 ****
struct page *topage = virt_to_page(to);
!
set_bit(PG_mapped, &topage->flags);
--- 336,359 ----
struct page *topage = virt_to_page(to);
! #if XCHAL_DCACHE_IS_WRITEBACK
! unsigned long flags;
!
! /* 03mar2003 jn
! * I had a dream last night.... And in that dream I saw
! * a process being copied... But the the page "from" which
! * that process was being copied was an alias to the physical
! * page. And with cache aliasing, the data that was being
! * read was not in sync...
! * Therefore, at this point, we need to flush the writeback
! * cache before we do the copy.
! */
!
! save_and_cli(flags);
! xthal_dcache_all_writeback();
! restore_flags(flags);
!
! #endif
!
!
set_bit(PG_mapped, &topage->flags);
***************
*** 307,314 ****
copy_page(to, from);
} else {
- #if 0
- copy_page(to, from);
- flush_cache_all();
- #else
unsigned long new_to = (XTENSA_ALIAS_RESERVE_START);
unsigned long vpnval;
--- 361,364 ----
***************
*** 320,326 ****
down(&dealias_page_sem);
write_dtlb_entry(pteval, vpnval);
copy_page((void *)new_to, from);
! up(&dealias_page_sem);
#endif
}
}
--- 370,393 ----
down(&dealias_page_sem);
write_dtlb_entry(pteval, vpnval);
+ #if 0
+ printk("copy_user_page: to: %p\n", to);
+ printk(" from: %p\n", from);
+ printk(" new_to: %p\n", new_to);
+ printk(" address: %p\n", address);
+ #endif
+
copy_page((void *)new_to, from);
!
! /* XTFIXME -- would it be better to allocate the
! * new_to pte as writethru, instead of
! * having to writeback the cache at this
! * point?
! */
! #if XCHAL_DCACHE_IS_WRITEBACK
! save_and_cli(flags);
! xthal_dcache_all_writeback();
! restore_flags(flags);
#endif
+ up(&dealias_page_sem);
}
}
***************
*** 336,343 ****
#endif /* XTENSA_CACHE_ALIAS */
-
-
-
-
-
--- 403,405 ----
Index: fault.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/fault.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** fault.c 28 Feb 2003 01:53:09 -0000 1.5
--- fault.c 5 Mar 2003 17:57:44 -0000 1.6
***************
*** 68,72 ****
save_and_cli(flags);
#if ( XCHAL_DCACHE_IS_WRITEBACK )
! xthal_dcache_region_writeback(ptep, 4);
#endif
xthal_dcache_line_invalidate(ptevaddr);
--- 68,72 ----
save_and_cli(flags);
#if ( XCHAL_DCACHE_IS_WRITEBACK )
! xthal_dcache_line_writeback(ptep);
#endif
xthal_dcache_line_invalidate(ptevaddr);
***************
*** 74,77 ****
--- 74,78 ----
#endif
save_and_cli(flags);
+ xthal_dcache_all_writeback();
xthal_dcache_all_invalidate();
restore_flags(flags);
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** mmu.c 28 Feb 2003 01:53:09 -0000 1.6
--- mmu.c 5 Mar 2003 17:57:45 -0000 1.7
***************
*** 24,27 ****
--- 24,28 ----
/* Called from arch-indep. files: */
+
void flush_tlb_all (void)
{
***************
*** 90,93 ****
--- 91,97 ----
unsigned long flags;
int oldpid;
+
+ // !!!!
+ flush_cache_all();
#ifdef DEBUG_TLB
|
|
From: <za...@us...> - 2003-03-04 07:39:34
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv16720
Modified Files:
process.c
Log Message:
The indices when copying aregs were wrong.
Index: process.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/process.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** process.c 14 Feb 2003 18:48:10 -0000 1.10
--- process.c 4 Mar 2003 07:39:31 -0000 1.11
***************
*** 289,298 ****
for (i = 0; i < regs->wmask * 4; i+=4) {
/* using wb_offset as window-pane number */
! if (--wb_offset < 0)
! wb_offset = XCHAL_NUM_AREGS / 4;
! elfregs->ar[wb_offset + 0] = tsk->thread.regfile[i*4 + 0];
! elfregs->ar[wb_offset + 1] = tsk->thread.regfile[i*4 + 1];
! elfregs->ar[wb_offset + 2] = tsk->thread.regfile[i*4 + 2];
! elfregs->ar[wb_offset + 3] = tsk->thread.regfile[i*4 + 3];
}
}
--- 289,298 ----
for (i = 0; i < regs->wmask * 4; i+=4) {
/* using wb_offset as window-pane number */
! if ((wb_offset -= 4) < 0)
! wb_offset = XCHAL_NUM_AREGS - 4;
! elfregs->ar[wb_offset + 0] = tsk->thread.regfile[i + 0];
! elfregs->ar[wb_offset + 1] = tsk->thread.regfile[i + 1];
! elfregs->ar[wb_offset + 2] = tsk->thread.regfile[i + 2];
! elfregs->ar[wb_offset + 3] = tsk->thread.regfile[i + 3];
}
}
***************
*** 339,348 ****
for (i = 0; i < regs->wmask * 4; i+=4) {
/* using wb_offset as window-pane number */
! if (--wb_offset < 0)
! wb_offset = XCHAL_NUM_AREGS / 4;
! tsk->thread.regfile[i*4 + 0] = elfregs->ar[wb_offset + 0];
! tsk->thread.regfile[i*4 + 1] = elfregs->ar[wb_offset + 1];
! tsk->thread.regfile[i*4 + 2] = elfregs->ar[wb_offset + 2];
! tsk->thread.regfile[i*4 + 3] = elfregs->ar[wb_offset + 3];
}
}
--- 339,348 ----
for (i = 0; i < regs->wmask * 4; i+=4) {
/* using wb_offset as window-pane number */
! if ((wb_offset -= 4) < 0)
! wb_offset = XCHAL_NUM_AREGS - 4;
! tsk->thread.regfile[i + 0] = elfregs->ar[wb_offset + 0];
! tsk->thread.regfile[i + 1] = elfregs->ar[wb_offset + 1];
! tsk->thread.regfile[i + 2] = elfregs->ar[wb_offset + 2];
! tsk->thread.regfile[i + 3] = elfregs->ar[wb_offset + 3];
}
}
|
|
From: <jn...@us...> - 2003-03-01 03:02:51
|
Update of /cvsroot/xtensa/linux/arch/xtensa/boot/boot-redboot In directory sc8-pr-cvs1:/tmp/cvs-serv23639 Modified Files: bootstrap.S Log Message: Fixed a bug that where the kernel wouldn't always boot when writeback caches were enabled. This is the "it works every other time bug." Now it should work every time. Index: bootstrap.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/boot/boot-redboot/bootstrap.S,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** bootstrap.S 28 Aug 2002 16:10:13 -0000 1.1.1.1 --- bootstrap.S 1 Mar 2003 03:02:46 -0000 1.2 *************** *** 3,6 **** --- 3,7 ---- #include <xtensa/config/specreg.h> #include <xtensa/config/core.h> + #include <xtensa/cacheasm.h> /* * RB-Data: RedBoot data/bss *************** *** 66,69 **** --- 67,71 ---- /* XTFIXME workaround (bug in assembler: addi a0, a0, ... doesn't work) */ + addi a4, a0, __start - __start_a0 mov.n a0, a4 *************** *** 91,102 **** blt a8, a5, 1b - ## XTFIXME: flush d-caches (WB-caches) ! /* invalidate i-caches */ ! ! mov.n a6, a0 ! 2: dhi a6, 0 ! addi a6, a6, XCHAL_ICACHE_LINESIZE ! blt a6, a5, 2b movi a11, _reloc --- 93,107 ---- blt a8, a5, 1b ! /* 28feb2003 jn -- ! * I changed this to use the nice macros provided, it's ! * a bit of overkill because you don't really need to flush ! * the entire cache, just the regions to where we just copied ! * the code. ! */ ! #if XCHAL_DCACHE_IS_WRITEBACK ! dcache_writeback_all a5, a6 ! #endif ! icache_invalidate_all a5, a6 movi a11, _reloc *************** *** 166,169 **** --- 171,183 ---- /* jump to the kernel */ + + + /* 28feb2003 -- jn + * we just copied the kernel, it might be wise + * at this point to flush the caches, no? + */ + dcache_writeback_all a5, a6 + icache_invalidate_all a5, a6 + /* movi a2, _param_start */ |
|
From: <jn...@us...> - 2003-02-28 23:18:56
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv8277
Modified Files:
cache.c
Log Message:
Fixed a couple more occurrences of XCHALDCACHE where it
should have been XCHAL_DCACHE. The affected regions of
code worked regardless though, because on the current
Xtensa implementation, the dcache_region_writeback_inv
and dcache_region_invalidate do exactly the same thing.
Index: cache.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/cache.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** cache.c 28 Feb 2003 22:59:36 -0000 1.6
--- cache.c 28 Feb 2003 23:18:49 -0000 1.7
***************
*** 205,209 ****
unsigned long flags;
save_and_cli(flags);
! #if defined(XCHALDCACHE_IS_WRITEBACK)
xthal_dcache_region_writeback_inv((void *)start, end - start);
#else
--- 205,209 ----
unsigned long flags;
save_and_cli(flags);
! #if defined(XCHAL_DCACHE_IS_WRITEBACK)
xthal_dcache_region_writeback_inv((void *)start, end - start);
#else
***************
*** 254,258 ****
save_and_cli(flags);
#if 1
! #if defined(XCHALDCACHE_IS_WRITEBACK)
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
#else
--- 254,258 ----
save_and_cli(flags);
#if 1
! #if defined(XCHAL_DCACHE_IS_WRITEBACK)
xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
#else
|
|
From: <jn...@us...> - 2003-02-28 22:59:42
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv32164
Modified Files:
cache.c
Log Message:
Moved flush_dcache_page so that it is compiled away when
there is no cache aliasing.
Fixed a typo so that the icache flush functions are there
for writeback caches.
Index: cache.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/cache.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** cache.c 28 Feb 2003 01:53:09 -0000 1.5
--- cache.c 28 Feb 2003 22:59:36 -0000 1.6
***************
*** 188,192 ****
*/
! #if (XTENSA_CACHE_ALIAS || XCHALDCACHE_IS_WRITEBACK)
void flush_page_to_ram (struct page *page)
--- 188,192 ----
*/
! #if (XTENSA_CACHE_ALIAS || XCHAL_DCACHE_IS_WRITEBACK)
void flush_page_to_ram (struct page *page)
***************
*** 200,224 ****
- void flush_dcache_page (struct page *page)
- {
- unsigned long addr = (unsigned long) page_address(page);
- unsigned long flags;
- save_and_cli(flags);
- #if 1
- #if defined(XCHALDCACHE_IS_WRITEBACK)
- xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
- #else
- xthal_dcache_region_invalidate((void *)addr, PAGE_SIZE);
- #endif
- #else
- /* XTFIXME -- this is just a test, going to flush the entire cache
- * cache and see if that makes it start working.
- */
- // printk("flush_dcache_page: addr=0x%08x\n", addr);
- xthal_dcache_all_writeback_inv();
- #endif
-
- restore_flags(flags);
- }
void flush_icache_range(unsigned long start, unsigned long end)
--- 200,203 ----
***************
*** 268,271 ****
--- 247,272 ----
*/
#if XTENSA_CACHE_ALIAS
+
+ void flush_dcache_page (struct page *page)
+ {
+ unsigned long addr = (unsigned long) page_address(page);
+ unsigned long flags;
+ save_and_cli(flags);
+ #if 1
+ #if defined(XCHALDCACHE_IS_WRITEBACK)
+ xthal_dcache_region_writeback_inv((void *)addr, PAGE_SIZE);
+ #else
+ xthal_dcache_region_invalidate((void *)addr, PAGE_SIZE);
+ #endif
+ #else
+ /* XTFIXME -- this is just a test, going to flush the entire cache
+ * cache and see if that makes it start working.
+ */
+ // printk("flush_dcache_page: addr=0x%08x\n", addr);
+ xthal_dcache_all_writeback_inv();
+ #endif
+
+ restore_flags(flags);
+ }
static struct semaphore dealias_page_sem;
|
|
From: <jn...@us...> - 2003-02-28 01:53:27
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv6560/arch/xtensa/kernel
Modified Files:
setup.c sysxtensa.c
Log Message:
Added support for caches that have "ways" larger than PAGE_SIZE.
This was mostly copied from the sh-4 port which suffers from the
same feature. There are still some optimizations that can be done
with regard to defering some cache flusing, and reducing some complete
cache flushes to flushes of the appropriate cache lines.
When the cache way size is less than or equal to PAGE_SIZE, all
of these changes should be optimized away, and the port should run
exactly as it did prior to these changes.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/setup.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** setup.c 15 Feb 2003 01:39:31 -0000 1.8
--- setup.c 28 Feb 2003 01:53:09 -0000 1.9
***************
*** 40,43 ****
--- 40,44 ----
#include <asm/timex.h>
#include <asm/machvec.h>
+ #include <asm/page.h>
#include <asm/platform/hardware.h>
***************
*** 295,298 ****
--- 296,302 ----
extern int mem_reserve(unsigned long, unsigned long, int);
extern void memory_init(void);
+ #if XTENSA_CACHE_ALIAS
+ extern void xtensa_cache_init(void);
+ #endif
memcpy(saved_command_line, command_line, CL_SIZE);
***************
*** 346,349 ****
--- 350,357 ----
/* Register panic handler, for debugging purposes only: */
notifier_chain_register(&panic_notifier_list, &xtensa_panic_block);
+ #endif
+
+ #if XTENSA_CACHE_ALIAS
+ xtensa_cache_init();
#endif
}
Index: sysxtensa.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/sysxtensa.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** sysxtensa.c 28 Aug 2002 16:10:14 -0000 1.1.1.1
--- sysxtensa.c 28 Feb 2003 01:53:09 -0000 1.2
***************
*** 15,21 ****
--- 15,26 ----
#include <linux/errno.h>
#include <linux/sched.h>
+ #include <linux/mm.h>
#include <asm/sysxtensa.h>
#include <asm/uaccess.h>
#include <asm/xtutil.h>
+ #include <asm/mman.h>
+ #include <asm/shmparam.h>
+ #include <asm/page.h>
+
***************
*** 67,70 ****
--- 72,165 ----
return retval;
}
+
+
+
+ /* 19feb2003 jn
+ * Some versions of xtensa don't have cache alias'ing problems (or benefits)
+ * so, we only include this code if it is actually required.
+ *
+ * This function was borrowed from the very nice folks at SH
+ * and I would like to thank the SH engineers for also having this
+ * cache aliasing problem (or benefit).
+ */
+
+ #if XTENSA_CACHE_ALIAS
+
+ /*
+ * To avoid cache alias, we map all shared pages with same color.
+ *
+ * 19feb2003 -- jn
+ * (this seems a bit restrictive to me, but it will do for now)
+ */
+ #define COLOUR_ALIGN(addr) (( (addr)+SHMLBA-1) & ~(SHMLBA-1) )
+
+ unsigned long arch_get_unmapped_area(
+ struct file *filp,
+ unsigned long addr,
+ unsigned long len,
+ unsigned long pgoff,
+ unsigned long flags)
+ {
+ struct vm_area_struct *vma;
+
+ if (flags & MAP_FIXED) {
+ /* We do not accept a shared mapping if it would violate
+ * cache aliasing constraints.
+ */
+ if ((flags & MAP_SHARED) && (addr & (SHMLBA - 1))) {
+ printk("arch_get_unmapped_area: violoates shared mapping...\n");
+ return -EINVAL;
+ }
+ printk("arch_get_unmapped_area: violoates shared mapping...\n");
+ return addr;
+ }
+
+
+ if (len > TASK_SIZE) {
+ printk("arch_get_unmapped_area: len > TASK_SIZE\n");
+ return -ENOMEM;
+ }
+
+
+ if (!addr) {
+ addr = TASK_UNMAPPED_BASE;
+ }
+
+
+ if (flags & MAP_PRIVATE) {
+ // printk("arch_get_unmapped_area: requesting private area.\n");
+ addr = PAGE_ALIGN(addr);
+ } else {
+ addr = COLOUR_ALIGN(addr);
+ }
+
+ for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {
+ /* At this point: (!vma || addr < vma->vm_end). */
+ if (TASK_SIZE - len < addr) {
+ printk("arch_get_unmapped_area: no memory avail...\n");
+ return -ENOMEM;
+ }
+
+ if (!vma || addr + len <= vma->vm_start)
+ {
+ // printk("arch_get_unmapped_area returns: 0x%08x\n", addr);
+ return addr;
+ }
+
+ addr = vma->vm_end;
+
+ /* if we are not mapping private, then do the colour align thingy */
+ if (! (flags & MAP_PRIVATE) )
+ addr = COLOUR_ALIGN(addr);
+ #if 0
+ else
+ printk("arch_get_unmapped_area -- looking for a private area.\n");
+ #endif
+ }
+ }
+ #endif
+
+
+
/*
|
