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From: <joe...@us...> - 2003-04-23 00:36:30
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv28811/arch/xtensa/kernel
Modified Files:
signal.c
Log Message:
Rework the sigframe structures so they properly account for the base save area of the user's stack.
Index: signal.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/signal.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** signal.c 22 Apr 2003 21:36:13 -0000 1.5
--- signal.c 23 Apr 2003 00:36:27 -0000 1.6
***************
*** 31,40 ****
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
- /*
- * Number of bytes reserved below the stack pointer
- * (16 bytes for caller's a0-a3 save area, 16 bytes for misc
- * uses such as nested C function call chain pointer: */
- #define XTENSA_RESERVED_BELOW_SP 32
-
asmlinkage long sys_wait4(pid_t pid,unsigned int * stat_addr, int options, struct rusage * ru);
asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset);
--- 31,34 ----
***************
*** 176,193 ****
struct sigframe
{
- unsigned int window[4]; /* Window of 4 registers for initial context */
- unsigned int reserved[4]; /* Reserved area for chaining */
struct sigcontext sc;
unsigned long extramask[_NSIG_WORDS-1];
unsigned char retcode[6];
};
struct rt_sigframe
{
- unsigned int window[4]; /* Window of 4 registers for initial context */
- unsigned int reserved[4]; /* Reserved area for chaining */
struct siginfo info;
struct ucontext uc;
unsigned char retcode[6];
};
--- 170,187 ----
struct sigframe
{
struct sigcontext sc;
unsigned long extramask[_NSIG_WORDS-1];
unsigned char retcode[6];
+ unsigned int window[4]; /* Window of 4 registers for initial context */
+ unsigned int reserved[4]; /* Reserved area for chaining */
};
struct rt_sigframe
{
struct siginfo info;
struct ucontext uc;
unsigned char retcode[6];
+ unsigned int window[4]; /* Window of 4 registers for initial context */
+ unsigned int reserved[4]; /* Reserved area for chaining */
};
***************
*** 408,413 ****
if ((ka->sa.sa_flags & SA_ONSTACK) != 0 && ! on_sig_stack(sp))
sp = current->sas_ss_sp + current->sas_ss_size;
- else
- sp -= XTENSA_RESERVED_BELOW_SP;
return (void *)((sp - frame_size) & -16ul);
--- 402,405 ----
|
|
From: <ma...@us...> - 2003-04-22 21:36:17
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv25303 Modified Files: signal.c Log Message: Avoid overwriting the save area below user SP when generating signal frames. Index: signal.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/signal.c,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** signal.c 20 Mar 2003 20:41:09 -0000 1.4 --- signal.c 22 Apr 2003 21:36:13 -0000 1.5 *************** *** 31,34 **** --- 31,40 ---- #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) + /* + * Number of bytes reserved below the stack pointer + * (16 bytes for caller's a0-a3 save area, 16 bytes for misc + * uses such as nested C function call chain pointer: */ + #define XTENSA_RESERVED_BELOW_SP 32 + asmlinkage long sys_wait4(pid_t pid,unsigned int * stat_addr, int options, struct rusage * ru); asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset); *************** *** 402,405 **** --- 408,413 ---- if ((ka->sa.sa_flags & SA_ONSTACK) != 0 && ! on_sig_stack(sp)) sp = current->sas_ss_sp + current->sas_ss_size; + else + sp -= XTENSA_RESERVED_BELOW_SP; return (void *)((sp - frame_size) & -16ul); |
|
From: <ahe...@us...> - 2003-04-16 00:44:25
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv9705/arch/xtensa/kernel
Modified Files:
process.c
Log Message:
Added config option CONFIG_MULTITHREADED_CORES and dump_task_fpu() function.
Index: process.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/process.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** process.c 4 Mar 2003 07:39:31 -0000 1.11
--- process.c 16 Apr 2003 00:44:22 -0000 1.12
***************
*** 424,438 ****
/*
! * Fill in the CP structure for a core dump.
! * This includes any FPU coprocessor.
! * Here, we dump all coprocessors, and other ("extra") custom state.
! *
! * This function is called by elf_core_dump() in fs/binfmt_elf.c
! * (in which case 'regs' comes from calls to do_coredump, see signals.c).
*/
! int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
{
#if TOTAL_CPEXTRA_SIZE > 16 /* see asm/cpextra.h for this magic number 16 */
! do_save_fpregs (r, regs, current); /* XTFIXME: will regs always be for current? */
/* For now, bit 16 means some extra state may be present: */
--- 424,433 ----
/*
! * Fill in the CP structure for a core dump for a particular task.
*/
! int dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r)
{
#if TOTAL_CPEXTRA_SIZE > 16 /* see asm/cpextra.h for this magic number 16 */
! do_save_fpregs (r, regs, task);
/* For now, bit 16 means some extra state may be present: */
***************
*** 441,444 ****
--- 436,452 ----
return 0; /* no coprocessors active on this processor */
#endif
+ }
+
+ /*
+ * Fill in the CP structure for a core dump.
+ * This includes any FPU coprocessor.
+ * Here, we dump all coprocessors, and other ("extra") custom state.
+ *
+ * This function is called by elf_core_dump() in fs/binfmt_elf.c
+ * (in which case 'regs' comes from calls to do_coredump, see signals.c).
+ */
+ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
+ {
+ return dump_task_fpu (regs, current, r);
}
|
|
From: <ahe...@us...> - 2003-04-16 00:44:25
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv9705/arch/xtensa Modified Files: config.in Log Message: Added config option CONFIG_MULTITHREADED_CORES and dump_task_fpu() function. Index: config.in =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/config.in,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** config.in 11 Mar 2003 21:52:33 -0000 1.5 --- config.in 16 Apr 2003 00:44:22 -0000 1.6 *************** *** 73,76 **** --- 73,77 ---- define_bool CONFIG_BINFMT_AOUT n define_bool CONFIG_BINFMT_ELF y + bool 'Support for ELF multithreaded core dumps' CONFIG_MULTITHREADED_CORES tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC bool 'Default bootloader kernel arguments' CONFIG_CMDLINE_BOOL |
|
From: <joe...@us...> - 2003-04-15 17:55:11
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv16642/arch/xtensa/kernel Modified Files: syscalls.h Log Message: sendfile has 4 args, not 3. Index: syscalls.h =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/syscalls.h,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** syscalls.h 1 Oct 2002 22:35:41 -0000 1.3 --- syscalls.h 15 Apr 2003 17:55:04 -0000 1.4 *************** *** 231,235 **** SYS(sys_capset, 2) /* 205 */ SYS(sys_sigaltstack, 0) ! SYS(sys_sendfile, 3) SYS(sys_ni_syscall, 0) SYS(sys_ni_syscall, 0) --- 231,235 ---- SYS(sys_capset, 2) /* 205 */ SYS(sys_sigaltstack, 0) ! SYS(sys_sendfile, 4) SYS(sys_ni_syscall, 0) SYS(sys_ni_syscall, 0) |
|
From: <jgr...@us...> - 2003-04-09 00:39:51
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv24020 Modified Files: xtensa_ksyms.c Log Message: Export __down_interruptible symbol for modules. Index: xtensa_ksyms.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/xtensa_ksyms.c,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** xtensa_ksyms.c 27 Mar 2003 19:42:46 -0000 1.4 --- xtensa_ksyms.c 9 Apr 2003 00:39:48 -0000 1.5 *************** *** 89,92 **** --- 89,93 ---- */ EXPORT_SYMBOL(__down); + EXPORT_SYMBOL(__down_interruptible); EXPORT_SYMBOL(__down_trylock); EXPORT_SYMBOL(__up); |
|
From: <joe...@us...> - 2003-04-03 18:48:11
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv17216/arch/xtensa/kernel
Modified Files:
setup.c
Log Message:
Change spaces to tabs due to peer pressure. Besides, everyone else is doing it. Just once won't hurt. If it feels good, do it. You'll be popular. :)
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/setup.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** setup.c 1 Apr 2003 22:08:12 -0000 1.10
--- setup.c 3 Apr 2003 18:48:05 -0000 1.11
***************
*** 367,383 ****
/* high-level stuff */
seq_printf ( f,
! "processor : 0\n"
! "vendor : Tensilica\n"
! "arch : Xtensa\n"
! "release : " XCHAL_HW_RELEASE_NAME "\n"
! "core ID : " XCHAL_CORE_ID "\n"
! "build ID : 0x%x\n"
#if XCHAL_HAVE_BE
! "endianness : big\n"
#else
! "endianness : little\n"
#endif
! "cpu MHz : %u.%02u\n"
! "bogomips : %lu.%02lu\n",
XCHAL_BUILD_UNIQUE_ID,
clock_tick_rate/1000000,
--- 367,383 ----
/* high-level stuff */
seq_printf ( f,
! "processor\t: 0\n"
! "vendor\t\t: Tensilica\n"
! "arch\t\t: Xtensa\n"
! "release\t\t: " XCHAL_HW_RELEASE_NAME "\n"
! "core ID\t\t: " XCHAL_CORE_ID "\n"
! "build ID\t: 0x%x\n"
#if XCHAL_HAVE_BE
! "endianness\t: big\n"
#else
! "endianness\t: little\n"
#endif
! "cpu MHz\t\t: %u.%02u\n"
! "bogomips\t: %lu.%02lu\n",
XCHAL_BUILD_UNIQUE_ID,
clock_tick_rate/1000000,
***************
*** 390,398 ****
seq_printf ( f,
#if XCHAL_HAVE_WINDOWED
! "windowed regs : yes\n"
#else
! "windowed regs : no\n"
#endif
! "physical aregs : %d\n", XCHAL_NUM_AREGS);
/* interrupts */
--- 390,398 ----
seq_printf ( f,
#if XCHAL_HAVE_WINDOWED
! "windowed regs\t: yes\n"
#else
! "windowed regs\t: no\n"
#endif
! "physical aregs\t: %d\n", XCHAL_NUM_AREGS);
/* interrupts */
***************
*** 401,417 ****
seq_printf ( f,
#if XCHAL_HAVE_HIGHLEVEL_INTERRUPTS
! "HL ints : yes\n"
#else
! "HL ints : no\n"
#endif
#if XCHAL_HAVE_NMI
! "NMI int : yes\n"
#else
! "NMI int : no\n"
#endif
! "num ints : %d\n"
! "ext ints : %d\n"
! "int levels : %d\n"
! "timers : %d\n",
XCHAL_NUM_INTERRUPTS,
XCHAL_NUM_EXTINTERRUPTS,
--- 401,417 ----
seq_printf ( f,
#if XCHAL_HAVE_HIGHLEVEL_INTERRUPTS
! "HL ints\t\t: yes\n"
#else
! "HL ints\t\t: no\n"
#endif
#if XCHAL_HAVE_NMI
! "NMI int\t\t: yes\n"
#else
! "NMI int\t\t: no\n"
#endif
! "num ints\t: %d\n"
! "ext ints\t: %d\n"
! "int levels\t: %d\n"
! "timers\t\t: %d\n",
XCHAL_NUM_INTERRUPTS,
XCHAL_NUM_EXTINTERRUPTS,
***************
*** 423,454 ****
seq_printf ( f,
#if XCHAL_HAVE_OCD
! "ocd : yes\n"
#else
! "ocd : no\n"
#endif
! "ibreaks : %d\n"
! "dbreaks : %d\n"
! "debug int : %d\n",
XCHAL_NUM_IBREAK,
XCHAL_NUM_DBREAK,
XCHAL_DEBUGLEVEL);
#else
! seq_printf ( f, "debug : no\n");
#endif /* XCHAL_HAVE_DEBUG */
/* coprocessors */
#if XCHAL_HAVE_CP
! seq_printf ( f, "coprocessors : %d\n", XCHAL_CP_NUM);
#else
! seq_printf ( f, "coprocessors : none\n");
#endif
/* {I,D}{RAM,ROM} and XLMI */
seq_printf ( f,
! "inst ROMs : %d\n"
! "inst RAMs : %d\n"
! "data ROMs : %d\n"
! "data RAMs : %d\n"
! "XLMI ports : %d\n",
XCHAL_NUM_IROM,
XCHAL_NUM_IRAM,
--- 423,454 ----
seq_printf ( f,
#if XCHAL_HAVE_OCD
! "ocd\t\t: yes\n"
#else
! "ocd\t\t: no\n"
#endif
! "ibreaks\t\t: %d\n"
! "dbreaks\t\t: %d\n"
! "debug int\t: %d\n",
XCHAL_NUM_IBREAK,
XCHAL_NUM_DBREAK,
XCHAL_DEBUGLEVEL);
#else
! seq_printf ( f, "debug\t\t: no\n");
#endif /* XCHAL_HAVE_DEBUG */
/* coprocessors */
#if XCHAL_HAVE_CP
! seq_printf ( f, "coprocessors\t: %d\n", XCHAL_CP_NUM);
#else
! seq_printf ( f, "coprocessors\t: none\n");
#endif
/* {I,D}{RAM,ROM} and XLMI */
seq_printf ( f,
! "inst ROMs\t: %d\n"
! "inst RAMs\t: %d\n"
! "data ROMs\t: %d\n"
! "data RAMs\t: %d\n"
! "XLMI ports\t: %d\n",
XCHAL_NUM_IROM,
XCHAL_NUM_IRAM,
***************
*** 459,482 ****
/* cache */
seq_printf ( f,
! "icache line size : %d\n"
! "icache ways : %d\n"
! "icache size : %d\n"
#if XCHAL_ICACHE_LINE_LOCKABLE
! "icache lockable : yes\n"
#else
! "icache lockable : no\n"
#endif
! "dcache line size : %d\n"
! "dcache ways : %d\n"
! "dcache size : %d\n"
#if XCHAL_DCACHE_IS_WRITEBACK
! "dcache writeback : yes\n"
#else
! "dcache writeback : no\n"
#endif
#if XCHAL_DCACHE_LINE_LOCKABLE
! "dcache lockable : yes\n"
#else
! "dcache lockable : no\n"
#endif
"",
--- 459,482 ----
/* cache */
seq_printf ( f,
! "icache line size: %d\n"
! "icache ways\t: %d\n"
! "icache size\t: %d\n"
#if XCHAL_ICACHE_LINE_LOCKABLE
! "icache lockable\t: yes\n"
#else
! "icache lockable\t: no\n"
#endif
! "dcache line size: %d\n"
! "dcache ways\t: %d\n"
! "dcache size\t: %d\n"
#if XCHAL_DCACHE_IS_WRITEBACK
! "dcache writeback: yes\n"
#else
! "dcache writeback: no\n"
#endif
#if XCHAL_DCACHE_LINE_LOCKABLE
! "dcache lockable\t: yes\n"
#else
! "dcache lockable\t: no\n"
#endif
"",
***************
*** 490,501 ****
/* MMU */
seq_printf ( f,
! "ASID bits : %d\n"
! "ASID invalid : %d\n"
! "ASID kernel : %d\n"
! "rings : %d\n"
! "itlb ways : %d\n"
! "itlb AR ways : %d\n"
! "dtlb ways : %d\n"
! "dtlb AR ways : %d\n",
XCHAL_MMU_ASID_BITS,
XCHAL_MMU_ASID_INVALID,
--- 490,501 ----
/* MMU */
seq_printf ( f,
! "ASID bits\t: %d\n"
! "ASID invalid\t: %d\n"
! "ASID kernel\t: %d\n"
! "rings\t\t: %d\n"
! "itlb ways\t: %d\n"
! "itlb AR ways\t: %d\n"
! "dtlb ways\t: %d\n"
! "dtlb AR ways\t: %d\n",
XCHAL_MMU_ASID_BITS,
XCHAL_MMU_ASID_INVALID,
***************
*** 510,578 ****
seq_printf ( f,
#if XCHAL_HAVE_DENSITY
! "code density : yes\n"
#else
! "code density : no\n"
#endif
#if XCHAL_HAVE_BOOLEANS
! "booleans : yes\n"
#else
! "booleans : no\n"
#endif
#if XCHAL_HAVE_LOOPS
! "loops : yes\n"
#else
! "loops : no\n"
#endif
#if XCHAL_HAVE_NSA
! "nsa : yes\n"
#else
! "nsa : no\n"
#endif
#if XCHAL_HAVE_MINMAX
! "min max : yes\n"
#else
! "min max : no\n"
#endif
#if XCHAL_HAVE_SEXT
! "sext : yes\n"
#else
! "sext : no\n"
#endif
#if XCHAL_HAVE_CLAMPS
! "clamps : yes\n"
#else
! "clamps : no\n"
#endif
#if XCHAL_HAVE_MAC16
! "mac16 : yes\n"
#else
! "mac16 : no\n"
#endif
#if XCHAL_HAVE_MUL16
! "mul16 : yes\n"
#else
! "mul16 : no\n"
#endif
#if XCHAL_HAVE_MUL32
! "mul32 : yes\n"
#else
! "mul32 : no\n"
#endif
#if XCHAL_HAVE_MUL32_HIGH
! "mul32 high : yes\n"
#else
! "mul32 high : no\n"
#endif
#if XCHAL_HAVE_FP
! "fpu : yes\n"
#else
! "fpu : no\n"
#endif
#if XCHAL_HAVE_SPECULATION
! "speculation : yes\n"
#else
! "speculation : no\n"
#endif
! "misc regs : %d\n",
XCHAL_NUM_MISC_REGS);
--- 510,578 ----
seq_printf ( f,
#if XCHAL_HAVE_DENSITY
! "code density\t: yes\n"
#else
! "code density\t: no\n"
#endif
#if XCHAL_HAVE_BOOLEANS
! "booleans\t: yes\n"
#else
! "booleans\t: no\n"
#endif
#if XCHAL_HAVE_LOOPS
! "loops\t\t: yes\n"
#else
! "loops\t\t: no\n"
#endif
#if XCHAL_HAVE_NSA
! "nsa\t\t: yes\n"
#else
! "nsa\t\t: no\n"
#endif
#if XCHAL_HAVE_MINMAX
! "min max\t\t: yes\n"
#else
! "min max\t\t: no\n"
#endif
#if XCHAL_HAVE_SEXT
! "sext\t\t: yes\n"
#else
! "sext\t\t: no\n"
#endif
#if XCHAL_HAVE_CLAMPS
! "clamps\t\t: yes\n"
#else
! "clamps\t\t: no\n"
#endif
#if XCHAL_HAVE_MAC16
! "mac16\t\t: yes\n"
#else
! "mac16\t\t: no\n"
#endif
#if XCHAL_HAVE_MUL16
! "mul16\t\t: yes\n"
#else
! "mul16\t\t: no\n"
#endif
#if XCHAL_HAVE_MUL32
! "mul32\t\t: yes\n"
#else
! "mul32\t\t: no\n"
#endif
#if XCHAL_HAVE_MUL32_HIGH
! "mul32 high\t: yes\n"
#else
! "mul32 high\t: no\n"
#endif
#if XCHAL_HAVE_FP
! "fpu\t\t: yes\n"
#else
! "fpu\t\t: no\n"
#endif
#if XCHAL_HAVE_SPECULATION
! "speculation\t: yes\n"
#else
! "speculation\t: no\n"
#endif
! "misc regs\t: %d\n",
XCHAL_NUM_MISC_REGS);
|
|
From: <joe...@us...> - 2003-04-03 04:12:39
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv15522/arch/xtensa/kernel Modified Files: sys.S Log Message: Correct a false assumption in a fixup routine. Load original WB/WS values for improved error reporting. Index: sys.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/sys.S,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** sys.S 21 Mar 2003 18:11:53 -0000 1.4 --- sys.S 3 Apr 2003 04:12:36 -0000 1.5 *************** *** 628,632 **** * When the double exception occurs: * - WB/WS are inconsistent ! * - WB is unmodified since .Lspill_loop * - a2 is the loop-control value of .Lspill_loop * - The .Lspill12 case of the .Lspill_loop presents a --- 628,632 ---- * When the double exception occurs: * - WB/WS are inconsistent ! * - WB is unmodified since the exception in .Lspill_loop * - a2 is the loop-control value of .Lspill_loop * - The .Lspill12 case of the .Lspill_loop presents a *************** *** 634,638 **** * * On Entry: ! * a0 contains DEPC * [EXCSAVE_1 + TABLE_SAVEA0] contains DEPC (same as a0) * DEPC contains a0 --- 634,638 ---- * * On Entry: ! * a0 is undefined * [EXCSAVE_1 + TABLE_SAVEA0] contains DEPC (same as a0) * DEPC contains a0 *************** *** 665,668 **** --- 665,669 ---- movi a2, .Lspill12 + l32i a0, a1, TABLE_SAVEA0 /* slot */ bltu a0, a2, 1f // branch if no adjustment needed *************** *** 853,861 **** movi a0, .Linvalid_window_string ! 1: rsr a4, WINDOWBASE // remember original WB in a4 ! rsr a3, WINDOWSTART // remember faulty WS in a3 ! /* First, ensure we have a valid WINDOWSTART value. */ ! rsr a2, WINDOWBASE // get (original) window base ssl a2 // setup for shift left by WINDOWBASE movi a2, 1 --- 854,863 ---- movi a0, .Linvalid_window_string ! 1: movi a2, quick_save_area ! l32i a4, a2, SAVE_WB // original WB ! l32i a3, a2, SAVE_WS // original WS ! /* Ensure we have a valid WINDOWSTART value. */ ! rsr a2, WINDOWBASE // get current window base ssl a2 // setup for shift left by WINDOWBASE movi a2, 1 |
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From: <joe...@us...> - 2003-04-03 04:07:46
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv14086/arch/xtensa/kernel
Modified Files:
traps.c
Log Message:
Enable handling of unaligned accesses originating from the kernel.
Also, clarify an error message.
Index: traps.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/traps.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -C2 -d -r1.12 -r1.13
*** traps.c 1 Apr 2003 22:31:27 -0000 1.12
--- traps.c 3 Apr 2003 04:07:43 -0000 1.13
***************
*** 318,322 ****
tsk->comm, regs->excvaddr, regs->pc,
(regs->aregs[0] & 0x3FFFFFFF) | (regs->pc & 0xC0000000) );
! panic ("Giving up on unaligned kernel access\n");
}
}
--- 318,322 ----
tsk->comm, regs->excvaddr, regs->pc,
(regs->aregs[0] & 0x3FFFFFFF) | (regs->pc & 0xC0000000) );
! panic ("Giving up due to unaligned kernel access\n");
}
}
***************
*** 438,442 ****
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
! /*set_except_vector(EXC_CODE_KERNEL + XCHAL_EXCCAUSE_UNALIGNED, handle_unaligned_kernel);*/ /*XTFIXME - turned off for debugging*/
set_c_except_handler (XCHAL_EXCCAUSE_UNALIGNED, handle_unaligned_user);
#endif
--- 438,442 ----
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
! set_except_vector(EXC_CODE_KERNEL + XCHAL_EXCCAUSE_UNALIGNED, handle_unaligned_kernel);
set_c_except_handler (XCHAL_EXCCAUSE_UNALIGNED, handle_unaligned_user);
#endif
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From: <ma...@us...> - 2003-04-01 22:31:30
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv798
Modified Files:
traps.c
Log Message:
Add multihit exception handler, to output better debugging data on multihit exceptions.
Index: traps.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/traps.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** traps.c 20 Mar 2003 20:49:08 -0000 1.11
--- traps.c 1 Apr 2003 22:31:27 -0000 1.12
***************
*** 6,15 ****
* for more details.
*
* Copyright (C) 1994 - 1999 by Ralf Baechle
* Modified for R3000 by Paul M. Antoine, 1995, 1996
* Complete output from die() by Ulf Carlsson, 1998
* Copyright (C) 1999 Silicon Graphics, Inc.
! * Copyright (C) 2001 - 2002 Tensilica Inc., by Joe Taylor, Kevin Chea,
! * Marc Gauthier, Scott Foehner
*/
--- 6,21 ----
* for more details.
*
+ * Derived from code with the following copyrights:
* Copyright (C) 1994 - 1999 by Ralf Baechle
* Modified for R3000 by Paul M. Antoine, 1995, 1996
* Complete output from die() by Ulf Carlsson, 1998
* Copyright (C) 1999 Silicon Graphics, Inc.
! *
! * Essentially rewritten for the Xtensa architecture port:
! * Copyright (C) 2001 - 2003 Tensilica Inc.
! * Author(s): Joe Taylor <jo...@te..., jo...@ya...>
! * Kevin Chea
! * Marc Gauthier <ma...@te...> <ma...@al...>
! * Scott Foehner <sfo...@ya...>
*/
***************
*** 150,153 ****
--- 156,173 ----
}
+ void do_multihit(struct pt_regs *regs)
+ {
+ extern void dump_all_tlbs(void);
+
+ /*
+ * This should never happen. Fatal.
+ */
+ dump_all_tlbs();
+ panic("Caught %s multihit exception at EXCVADDR=0x%08X - should not happen",
+ ((regs->exccause == XCHAL_EXCCAUSE_ITLB_MULTIHIT) ? "ITLB" : "DTLB"),
+ regs->excvaddr);
+ }
+
+
extern int do_set_xtrtctime(unsigned);
extern rwlock_t xtime_lock;
***************
*** 506,509 ****
--- 526,531 ----
set_c_except_handler (XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, do_page_fault);
set_c_except_handler (XCHAL_EXCCAUSE_DTLB_PRIVILEGE, do_page_fault);
+ set_c_except_handler (XCHAL_EXCCAUSE_ITLB_MULTIHIT, do_multihit);
+ set_c_except_handler (XCHAL_EXCCAUSE_DTLB_MULTIHIT, do_multihit);
set_c_except_handler (XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION,
handle_illegal_instruction);
|
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From: <ma...@us...> - 2003-04-01 22:30:39
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv651 Modified Files: handlers.S head.S Log Message: Fix multihit kernel bug -- essentially adjust pte_none() and related code. Index: handlers.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v retrieving revision 1.16 retrieving revision 1.17 diff -C2 -d -r1.16 -r1.17 *** handlers.S 29 Mar 2003 00:08:06 -0000 1.16 --- handlers.S 1 Apr 2003 22:30:29 -0000 1.17 *************** *** 2726,2729 **** --- 2726,2730 ---- pgd = pgd_offset (mm, regs->excvaddr); pmd = pmd_offset (pgd, regs->excvaddr); + pmdval = *pmd; */ *************** *** 2738,2764 **** _PMD_OFFSET a2, addr // empty macro, 2nd parm is optimized away ! /* We want to map the page of PTEs into the Page Table, but if ! * the task doesn't yet have a mapping for the region, just ! * map the exception_pte_table for the region. Note that we ! * do not modify the mappings for the task (tsk->mm->pgd) itself. ! * ! * exception_pte_table contains PTEs that will generate access ! * faults, and the exception will end up in do_page_fault() ! * for further handling. ! ! pmdval = *pmd; ! if (pmd_none(pmdval)) ! pmdval = __pmd((unsigned long)exception_pte_table); ! */ ! ! l32i a2, a2, 0 - movi a3, invalid_pte_table - movi a4, 0 - movi a5, 1 - sub a3, a2, a3 - moveqz a4, a5, a3 - movi a3, exception_pte_table - movnez a2, a3, a4 // a2 has appropriate pmdval /* Read ptevaddr and convert to top of page-table page. --- 2739,2744 ---- _PMD_OFFSET a2, addr // empty macro, 2nd parm is optimized away ! l32i a2, a2, 0 // read pmdval /* Read ptevaddr and convert to top of page-table page. *************** *** 2777,2783 **** movi a4, PAGE_MASK rsr a3, PTEVADDR // a3 = PTEVADDR - dsync - and a3, a4, a3 // a3 &= PAGE_MASK movi a5, -PAGE_OFFSET addi a3, a3, WIRED_WAY_FOR_PAGE_TABLE // a3 += way_number // a3 now has vpnval --- 2757,2762 ---- movi a4, PAGE_MASK rsr a3, PTEVADDR // a3 = PTEVADDR movi a5, -PAGE_OFFSET + and a3, a4, a3 // a3 &= PAGE_MASK addi a3, a3, WIRED_WAY_FOR_PAGE_TABLE // a3 += way_number // a3 now has vpnval *************** *** 2834,2839 **** * in kernel or user code, respectively, and then jump to the common * exception handling code. ! * Thus, rfi is usually never called for debug exceptions. Instead, ! * an rfe in the common exception path is called. * However, if PS.EXCM was set when the debug exception occurred, * it is handled differently; the exception is simply "ignored" --- 2813,2818 ---- * in kernel or user code, respectively, and then jump to the common * exception handling code. ! * Thus, RFI is usually never called for debug exceptions. Instead, ! * an RFE in the common exception path is called. * However, if PS.EXCM was set when the debug exception occurred, * it is handled differently; the exception is simply "ignored" Index: head.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/head.S,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** head.S 13 Feb 2003 19:32:02 -0000 1.5 --- head.S 1 Apr 2003 22:30:31 -0000 1.6 *************** *** 427,431 **** .comm swapper_pg_dir,PAGE_SIZE,PAGE_SIZE .comm invalid_pte_table,PAGE_SIZE,PAGE_SIZE - .comm exception_pte_table,PAGE_SIZE,PAGE_SIZE .comm empty_bad_page_table,PAGE_SIZE,PAGE_SIZE .comm empty_bad_page,PAGE_SIZE,PAGE_SIZE --- 427,430 ---- |
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From: <ma...@us...> - 2003-04-01 22:28:39
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv31532
Modified Files:
Makefile cache.c fault.c init.c mmu.c
Added Files:
mmu_dump.c
Log Message:
Fix multihit kernel bug -- essentially adjust pte_none() and related code.
Also separate out MMU dump code, and other sundry cleanup.
--- NEW FILE: mmu_dump.c ---
/*
* arch/xtensa/mm/mmu_dump.c
*
* Code to dump the contents of the MMU.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002 - 2003 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
* Marc Gauthier <ma...@te...> <ma...@al...>
*/
#include <xtensa/config/core.h>
//#include <linux/sched.h> /* asm/pgtable needs this (FIXME!?) */
#include <asm/pgtable.h>
#define XTENSA_MMU_DUMP 1
#if XTENSA_MMU_DUMP == 1
#define USE_ITLB 0
#define USE_DTLB 1
struct way_config_t {
int indicies;
int indicies_log2;
int pgsz_log2;
int arf;
};
static struct way_config_t itlb[XCHAL_ITLB_WAYS] =
{
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ARF)
},
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ARF)
},
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ARF)
},
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ARF)
},
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ARF)
},
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ARF)
},
{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES_LOG2),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, PAGESZ_LOG2_MIN),
XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ARF)
}
};
static struct way_config_t dtlb[XCHAL_DTLB_WAYS] =
{
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF)
},
{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES_LOG2),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, PAGESZ_LOG2_MIN),
XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ARF)
}
};
/* Total number of entries: */
#define ITLB_TOTAL_ENTRIES \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES) + \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES) + \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES) + \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES) + \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES) + \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES) + \
XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES)
#define DTLB_TOTAL_ENTRIES \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES) + \
XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES)
typedef struct {
unsigned va;
unsigned pa;
unsigned char asid;
unsigned char ca;
unsigned char way;
unsigned char index;
unsigned char pgsz_log2; /* 0 .. 32 */
unsigned char type; /* 0=ITLB 1=DTLB */
} tlb_dump_entry_t;
/* Return -1 if a precedes b, +1 if a follows b, 0 if same: */
int cmp_tlb_dump_info( tlb_dump_entry_t *a, tlb_dump_entry_t *b )
{
if (a->asid < b->asid) return -1;
if (a->asid > b->asid) return 1;
if (a->va < b->va) return -1;
if (a->va > b->va) return 1;
if (a->pa < b->pa) return -1;
if (a->pa > b->pa) return 1;
if (a->ca < b->ca) return -1;
if (a->ca > b->ca) return 1;
if (a->way < b->way) return -1;
if (a->way > b->way) return 1;
if (a->index < b->index) return -1;
if (a->index > b->index) return 1;
return 0;
}
void sort_tlb_dump_info( tlb_dump_entry_t *t, int n )
{
int i, j;
/* Simple O(n*n) sort: */
for (i = 0; i < n-1; i++)
for (j = i+1; j < n; j++)
if (cmp_tlb_dump_info(t+i, t+j) > 0) {
tlb_dump_entry_t tmp = t[i];
t[i] = t[j];
t[j] = tmp;
}
}
static tlb_dump_entry_t itlb_dump_info[ITLB_TOTAL_ENTRIES];
static tlb_dump_entry_t dtlb_dump_info[DTLB_TOTAL_ENTRIES];
static inline char *way_type (int type)
{
return type ? "autorefill" : "non-autorefill";
}
void print_entry (struct way_config_t *way_info,
unsigned int way,
unsigned int index,
unsigned int virtual,
unsigned int translation)
{
char valid_chr;
unsigned int va, pa, asid, ca;
va = virtual & ~((1 << (way_info->pgsz_log2 + way_info->indicies_log2)) - 1);
asid = virtual & ((1 << XCHAL_MMU_ASID_BITS) - 1);
pa = translation & ~((1 << way_info->pgsz_log2) - 1);
ca = translation & ((1 << XCHAL_MMU_CA_BITS) - 1);
valid_chr = asid ? 'V' : 'I';
/* Compute and incorporate the effect of the index bits on the
* va. It's more useful for kernel debugging, since we always
* want to know the effective va anyway. */
va += index << way_info->pgsz_log2;
printk ("\t[%d,%d] (%c) vpn 0x%.8x ppn 0x%.8x asid 0x%.2x am 0x%x\n",
way, index, valid_chr, va, pa, asid, ca);
}
void print_itlb_entry (struct way_config_t *way_info, int way, int index)
{
print_entry (way_info, way, index,
read_itlb_virtual (way + (index << way_info->pgsz_log2)),
read_itlb_translation (way + (index << way_info->pgsz_log2)));
}
void print_dtlb_entry (struct way_config_t *way_info, int way, int index)
{
print_entry (way_info, way, index,
read_dtlb_virtual (way + (index << way_info->pgsz_log2)),
read_dtlb_translation (way + (index << way_info->pgsz_log2)));
}
void dump_itlb (void)
{
int way, index;
printk ("\nITLB: ways = %d\n", XCHAL_ITLB_WAYS);
for (way = 0; way < XCHAL_ITLB_WAYS; way++) {
printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
way, itlb[way].indicies,
itlb[way].pgsz_log2, way_type(itlb[way].arf));
for (index = 0; index < itlb[way].indicies; index++) {
print_itlb_entry(&itlb[way], way, index);
}
}
}
void dump_dtlb (void)
{
int way, index;
printk ("\nDTLB: ways = %d\n", XCHAL_DTLB_WAYS);
for (way = 0; way < XCHAL_DTLB_WAYS; way++) {
printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
way, dtlb[way].indicies,
dtlb[way].pgsz_log2, way_type(dtlb[way].arf));
for (index = 0; index < dtlb[way].indicies; index++) {
print_dtlb_entry(&dtlb[way], way, index);
}
}
}
void dump_tlb (tlb_dump_entry_t *tinfo, struct way_config_t *config,
int entries, int ways, int type, int show_invalid)
{
tlb_dump_entry_t *e = tinfo;
int way, i;
/* Gather all info: */
for (way = 0; way < ways; way++) {
struct way_config_t *cfg = config + way;
for (i = 0; i < cfg->indicies; i++) {
unsigned wayindex = way + (i << cfg->pgsz_log2);
unsigned vv = (type ? read_dtlb_virtual (wayindex)
: read_itlb_virtual (wayindex));
unsigned pp = (type ? read_dtlb_translation (wayindex)
: read_itlb_translation (wayindex));
/* Compute and incorporate the effect of the index bits on the
* va. It's more useful for kernel debugging, since we always
* want to know the effective va anyway. */
e->va = (vv & ~((1 << (cfg->pgsz_log2 + cfg->indicies_log2)) - 1));
e->va += (i << cfg->pgsz_log2);
e->pa = (pp & ~((1 << cfg->pgsz_log2) - 1));
e->asid = (vv & ((1 << XCHAL_MMU_ASID_BITS) - 1));
e->ca = (pp & ((1 << XCHAL_MMU_CA_BITS) - 1));
e->way = way;
e->index = i;
e->pgsz_log2 = cfg->pgsz_log2;
e->type = type;
e++;
}
}
/* Sort by ASID and VADDR: */
sort_tlb_dump_info (tinfo, entries);
/* Display all sorted info: */
printk ("\n%cTLB dump:\n", (e->type ? 'D' : 'I'));
for (e = tinfo, i = 0; i < entries; i++, e++) {
if (e->asid == 0 && !show_invalid)
continue;
printk ("%c way=%d i=%d ASID=%02X V=%08X -> P=%08X CA=%X (%d %cB)\n",
(e->type ? 'D' : 'I'), e->way, e->index,
e->asid, e->va, e->pa, e->ca,
(1 << (e->pgsz_log2 % 10)),
" kMG"[e->pgsz_log2 / 10]
);
}
}
void dump_tlbs2 (int showinv)
{
dump_tlb (itlb_dump_info, itlb, ITLB_TOTAL_ENTRIES, XCHAL_ITLB_WAYS, 0, showinv);
dump_tlb (dtlb_dump_info, dtlb, DTLB_TOTAL_ENTRIES, XCHAL_DTLB_WAYS, 1, showinv);
}
void dump_all_tlbs (void)
{
dump_tlbs2 (1);
}
void dump_valid_tlbs (void)
{
dump_tlbs2 (0);
}
void dump_tlbs (void)
{
dump_itlb();
dump_dtlb();
}
#endif /* XTENSA_MMU_DUMP == 1 */
Index: Makefile
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** Makefile 17 Jan 2003 00:31:30 -0000 1.2
--- Makefile 1 Apr 2003 22:28:32 -0000 1.3
***************
*** 9,13 ****
O_TARGET := mm.o
! obj-y := extable.o init.o fault.o loadmmu.o mmu.o cache.o
include $(TOPDIR)/Rules.make
--- 9,13 ----
O_TARGET := mm.o
! obj-y := extable.o init.o fault.o loadmmu.o mmu.o cache.o mmu_dump.o
include $(TOPDIR)/Rules.make
Index: cache.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/cache.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** cache.c 5 Mar 2003 17:57:44 -0000 1.8
--- cache.c 1 Apr 2003 22:28:33 -0000 1.9
***************
*** 8,12 ****
* this archive for more details.
*
! * Copyright (C) 2003 Tensilica Inc. (by Joe Taylor, jo...@te...)
*/
--- 8,12 ----
* this archive for more details.
*
! * Copyright (C) 2001 - 2003 Tensilica Inc. (by Joe Taylor, jo...@te...)
*/
***************
*** 137,141 ****
* in the cache.
*/
! if (!(pte_val(*ptep) & _PAGE_VALID))
goto out;
--- 137,141 ----
* in the cache.
*/
! if (!pte_valid(*ptep))
goto out;
Index: fault.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/fault.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** fault.c 5 Mar 2003 17:57:44 -0000 1.6
--- fault.c 1 Apr 2003 22:28:34 -0000 1.7
***************
*** 9,15 ****
*
* Copyright (C) 1995 Linus Torvalds
! * Copyright (C) 2001 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
! * Marc Gauthier
* Kevin Chea
*/
--- 9,15 ----
*
* Copyright (C) 1995 Linus Torvalds
! * Copyright (C) 2001 - 2003 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
! * Marc Gauthier <ma...@te...> <ma...@al...>
* Kevin Chea
*/
***************
*** 85,88 ****
--- 85,100 ----
+ /* Define CATCH_NO_TLB_CLEAR to have a place for a breakpoint
+ * (in xt_staletlb()) for catching cases where do_page_fault() doesn't
+ * clear invalid TLB entries. This is purely for debugging. */
+ #undef CATCH_NO_TLB_CLEAR
+ #ifdef CATCH_NO_TLB_CLEAR
+ void xt_staletlb(void) {
+ }
+ #else
+ # define xt_staletlb() do {} while(0)
+ #endif
+
+
/*
* do_page_fault() could handle:
***************
*** 99,103 ****
*/
-
/*
* Macro for exception fixup code to access integer registers.
--- 111,114 ----
***************
*** 151,157 ****
* pte_alloc() and get_pte_slow() for more details. */
! if (pte_none(*pte)) {
invalidate_itlb_mapping(address);
}
write = 2; /* i-fetch */
--- 162,169 ----
* pte_alloc() and get_pte_slow() for more details. */
! if (!pte_valid(*pte)) {
invalidate_itlb_mapping(address);
}
+ else xt_staletlb();
write = 2; /* i-fetch */
***************
*** 170,177 ****
/* XXX -- jn */
! flush_pte_from_cache(pte, regs->excvaddr);
! // flush_cache_all();
return;
}
write = 2; /* i-fetch */
break;
--- 182,194 ----
/* XXX -- jn */
! flush_pte_from_cache(pte, address);
return;
}
+ xt_staletlb();
+ #define ALWAYS_INVAL 0
+ #if ALWAYS_INVAL
+ if (!pte_valid(*pte))
+ invalidate_itlb_mapping(address);
+ #endif
write = 2; /* i-fetch */
break;
***************
*** 189,196 ****
/* xxx jn */
! flush_pte_from_cache(pte, regs->excvaddr);
! // flush_cache_all();
return;
}
write = 0;
break;
--- 206,217 ----
/* xxx jn */
! flush_pte_from_cache(pte, address);
return;
}
+ xt_staletlb();
+ #if ALWAYS_INVAL
+ if (!pte_valid(*pte))
+ invalidate_dtlb_mapping(address);
+ #endif
write = 0;
break;
***************
*** 207,214 ****
/* xxx jn */
! flush_pte_from_cache(pte, regs->excvaddr);
! // flush_cache_all();
return;
}
write = 1;
break;
--- 228,239 ----
/* xxx jn */
! flush_pte_from_cache(pte, address);
return;
}
+ xt_staletlb();
+ #if ALWAYS_INVAL
+ if (!pte_valid(*pte))
+ invalidate_dtlb_mapping(address);
+ #endif
write = 1;
break;
***************
*** 220,226 ****
* get_pte_slow() for more details. */
! if (pte_none(*pte)) {
invalidate_dtlb_mapping(address);
}
--- 245,252 ----
* get_pte_slow() for more details. */
! if (!pte_valid(*pte)) {
invalidate_dtlb_mapping(address);
}
+ else xt_staletlb();
***************
*** 396,400 ****
/* handle_2nd_level_miss may have mapped
! * exception_pte_table, so unmap it here. Also clean
* up any leftover mappings for this address that may
* be invalid.
--- 422,426 ----
/* handle_2nd_level_miss may have mapped
! * invalid_pte_table, so unmap it here. Also clean
* up any leftover mappings for this address that may
* be invalid.
***************
*** 419,422 ****
--- 445,451 ----
+
+ /* See comments for update_mmu_cache() in pgtable.h */
+
void update_mmu_cache(struct vm_area_struct * vma,
unsigned long address,
***************
*** 443,444 ****
--- 472,474 ----
invalidate_page_table();
}
+
Index: init.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/init.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** init.c 13 Feb 2003 18:19:21 -0000 1.5
--- init.c 1 Apr 2003 22:28:34 -0000 1.6
***************
*** 8,12 ****
* for more details.
*
! * Copyright (C) 2001 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
* Marc Gauthier
--- 8,12 ----
* for more details.
*
! * Copyright (C) 2001 - 2003 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
* Marc Gauthier
***************
*** 57,61 ****
* the MMU hardware to generate an exception if loading a value into a
* TLB (i.e., auto-refill). In other words, the MMU considers all PTE
! * values as valid.
*
* This comment documents two solutions (so we don't have to redesign
--- 57,61 ----
* the MMU hardware to generate an exception if loading a value into a
* TLB (i.e., auto-refill). In other words, the MMU considers all PTE
! * values as "valid" in the sense of allowing them to be in the TLBs.
*
* This comment documents two solutions (so we don't have to redesign
***************
*** 65,71 ****
*
* This solution clears all PTE values when it allocates a new page of
! * PTEs. When the MMU reads a PTE into a TLB (i.e., auto-refill), vpn
! * = 0, ppn = 0, ring level = 0, and ca = 0. This TLB entry is
! * invalid, though the MMU hardware considers it valid.
*
* The most-likely result is a Privilege Exception in user code
--- 65,72 ----
*
* This solution clears all PTE values when it allocates a new page of
! * PTEs. When the MMU reads such a PTE into a TLB (i.e., auto-refill):
! * vpn = 0, ppn = 0, asid = RASID[ring level = 0] = 1, and ca = 0.
! * This TLB entry is invalid, though the MMU hardware loads it into
! * the TLB.
*
* The most-likely result is a Privilege Exception in user code
***************
*** 97,101 ****
* (i.e., auto-refill), vpn = 0, ppn = 0, ring level = USER_RING, and
* ca = 0. This TLB entry is invalid, though the MMU hardware
! * considers it valid.
*
* A TLB hit on this invalid entry will result in a Cache Attribute
--- 98,102 ----
* (i.e., auto-refill), vpn = 0, ppn = 0, ring level = USER_RING, and
* ca = 0. This TLB entry is invalid, though the MMU hardware
! * loads it into the TLB.
*
* A TLB hit on this invalid entry will result in a Cache Attribute
***************
*** 231,239 ****
extern char empty_bad_page_table[PAGE_SIZE];
int i;
unsigned long tmp = pte_val(BAD_PAGE);
unsigned long page = (unsigned long) empty_bad_page_table;
! for (i = 0; i < PTRS_PER_PGD; i++)
empty_bad_page_table[i] = tmp;
--- 232,243 ----
extern char empty_bad_page_table[PAGE_SIZE];
+ /* XTFIXME: other architectures just zero this page,
+ * why are we different? please comment */
+
int i;
unsigned long tmp = pte_val(BAD_PAGE);
unsigned long page = (unsigned long) empty_bad_page_table;
! for (i = 0; i < PTRS_PER_PTE; i++)
empty_bad_page_table[i] = tmp;
***************
*** 285,289 ****
/*
! * Initialize new page directory with pointers to invalid ptes
*/
void pgd_init(unsigned long page)
--- 289,295 ----
/*
! * Initialize new page directory with pointers to invalid PTE table ptrs
! * (really gets passed a pgd_t*, which is treated here as pmd_t* because
! * of collapsing; a bit too confusing, needs some clarification).
*/
void pgd_init(unsigned long page)
***************
*** 296,299 ****
--- 302,306 ----
* has virtually indexed caches, configurations are currently
* constrained to avoid aliasing issues.
+ * XTFIXME: cache aliasing is now allowed; does that affect this code?
*/
p = (unsigned long *) page;
***************
*** 301,312 ****
while (p < end) {
! p[0] = (unsigned long) invalid_pte_table;
! p[1] = (unsigned long) invalid_pte_table;
! p[2] = (unsigned long) invalid_pte_table;
! p[3] = (unsigned long) invalid_pte_table;
! p[4] = (unsigned long) invalid_pte_table;
! p[5] = (unsigned long) invalid_pte_table;
! p[6] = (unsigned long) invalid_pte_table;
! p[7] = (unsigned long) invalid_pte_table;
p += 8;
}
--- 308,319 ----
while (p < end) {
! pmd_clear ((pmd_t*)&p[0]);
! pmd_clear ((pmd_t*)&p[1]);
! pmd_clear ((pmd_t*)&p[2]);
! pmd_clear ((pmd_t*)&p[3]);
! pmd_clear ((pmd_t*)&p[4]);
! pmd_clear ((pmd_t*)&p[5]);
! pmd_clear ((pmd_t*)&p[6]);
! pmd_clear ((pmd_t*)&p[7]);
p += 8;
}
***************
*** 314,341 ****
! void exc_pte_init (unsigned long page)
{
! unsigned long *p, *end;
!
! p = (unsigned long *) page;
! end = p + PTRS_PER_PTE;
!
! /* Initialize the page so each pte contains cache attributes
! that prevents any and all accesses. */
! while (p < end) {
! p[0] = (unsigned long) pgprot_val(PAGE_NONE);
! p[1] = (unsigned long) pgprot_val(PAGE_NONE);
! p[2] = (unsigned long) pgprot_val(PAGE_NONE);
! p[3] = (unsigned long) pgprot_val(PAGE_NONE);
! p[4] = (unsigned long) pgprot_val(PAGE_NONE);
! p[5] = (unsigned long) pgprot_val(PAGE_NONE);
! p[6] = (unsigned long) pgprot_val(PAGE_NONE);
! p[7] = (unsigned long) pgprot_val(PAGE_NONE);
! p += 8;
! }
}
/* mem_reserve(start, end, must_exist)
*
--- 321,348 ----
! /*
! * Clear every entry of a page table (so that pte_none() is true for each entry).
! * This prevents accesses using an appropriate PTE value
! * (see pgtable.h for details).
! */
! void pte_table_clear (pte_t *ptable)
{
! int i;
! for (i = 0; i < PTRS_PER_PTE/8; i++) {
! pte_clear (&ptable[0]);
! pte_clear (&ptable[1]);
! pte_clear (&ptable[2]);
! pte_clear (&ptable[3]);
! pte_clear (&ptable[4]);
! pte_clear (&ptable[5]);
! pte_clear (&ptable[6]);
! pte_clear (&ptable[7]);
! ptable += 8;
! }
}
+
/* mem_reserve(start, end, must_exist)
*
***************
*** 450,467 ****
{
unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
! unsigned long max_dma, low;
int i;
/* Initialize the entire pgd. */
pgd_init((unsigned long)swapper_pg_dir);
- memset((void *)invalid_pte_table, 0, sizeof(pte_t) * PTRS_PER_PTE);
- /*MIPS did:*/
- /* pgd_init((unsigned long)swapper_pg_dir); */
- /* pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2); */
! /* Initialize exception_pte_table so each pte contains cache
! attributes that prevents any and all accesses. */
!
! exc_pte_init ((unsigned long)exception_pte_table);
#if 0
--- 457,467 ----
{
unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
! /*unsigned long max_dma, low;*/
int i;
/* Initialize the entire pgd. */
pgd_init((unsigned long)swapper_pg_dir);
! pte_table_clear (invalid_pte_table);
#if 0
***************
*** 482,490 ****
#endif
/*
* All pages are DMA-able so we put them all in the DMA zone.
*/
! zones_size[ZONE_DMA] = max_low_pfn;
! for (i = 1; i < MAX_NR_ZONES; i++)
zones_size[i] = 0;
free_area_init(zones_size);
--- 482,502 ----
#endif
/*
+ * Look in <linux/mmzone.h> for details. There are 3 zones:
+ * ZONE_DMA (DMA capable, directly mapped by kernel)
+ * ZONE_NORMAL (directly mapped by kernel)
+ * ZONE_HIGHMEM (dynamically mapped only)
+ *
* All pages are DMA-able so we put them all in the DMA zone.
+ * XTFIXME: memory past first physical 128 MB must be placed in ZONE_HIGHMEM
+ * (does Linux kernel support DMA capable memory in HIGHMEM?
+ * doesn't appear so...).
+ *
+ * NOTE: max_low_pfn is the same as max_pfn passed to init_bootmem()
+ * in memory_init() in this file. This is in turn dependent on
+ * the sysmem[] array initialized in init_arch() in setup.c.
*/
! for (i = 0; i < MAX_NR_ZONES; i++)
zones_size[i] = 0;
+ zones_size[ZONE_DMA] = max_low_pfn;
free_area_init(zones_size);
***************
*** 492,496 ****
--- 504,511 ----
+ #ifdef DEBUG_UNALIGNMENT_TEST
static void unaligned_test (void);
+ #endif
+
void debug_hooks (void)
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** mmu.c 31 Mar 2003 23:30:00 -0000 1.10
--- mmu.c 1 Apr 2003 22:28:34 -0000 1.11
***************
*** 8,14 ****
* for more details.
*
! * Copyright (C) 2001 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
! * Marc Gauthier
*/
--- 8,14 ----
* for more details.
*
! * Copyright (C) 2001 - 2003 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
! * Marc Gauthier <ma...@te...> <ma...@al...>
*/
***************
*** 212,231 ****
pgd = pgd_offset (mm, regs->excvaddr);
pmd = pmd_offset (pgd, regs->excvaddr);
-
- /* We want to map the page of PTEs into the Page Table, but if
- * the task doesn't yet have a mapping for the region, just
- * map the exception_pte_table for the region. Note that we
- * do not modify the mappings for the task (tsk->mm->pgd) itself.
- *
- * exception_pte_table contains PTEs that will generate access
- * faults, and the exception will end up in do_page_fault()
- * for further handling. */
-
pmdval = *pmd;
- if (pmd_none(pmdval))
- pmdval = __pmd((unsigned long)exception_pte_table);
/* read ptevaddr and convert to top of page-table page */
! vpnval = read_ptevaddr_register() & PAGE_MASK;
vpnval += WIRED_WAY_FOR_PAGE_TABLE; /* add way number for 'wdtlb' insn */
pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
--- 212,219 ----
pgd = pgd_offset (mm, regs->excvaddr);
pmd = pmd_offset (pgd, regs->excvaddr);
pmdval = *pmd;
/* read ptevaddr and convert to top of page-table page */
! vpnval = (read_ptevaddr_register() & PAGE_MASK);
vpnval += WIRED_WAY_FOR_PAGE_TABLE; /* add way number for 'wdtlb' insn */
pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
***************
*** 234,426 ****
-
- #define XT2000_MMU_DUMP 1
-
- #if (XT2000_MMU_DUMP == 1)
-
- #define USE_ITLB 0
- #define USE_DTLB 1
-
- struct way_config_t {
- int indicies;
- int indicies_log2;
- int pgsz_log2;
- int arf;
- };
-
- static struct way_config_t itlb[XCHAL_ITLB_WAYS] =
- {
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ARF)
- },
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ARF)
- },
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ARF)
- },
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ARF)
- },
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ARF)
- },
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ARF)
- },
- { XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES_LOG2),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, PAGESZ_LOG2_MIN),
- XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ARF)
- }
- };
-
- static struct way_config_t dtlb[XCHAL_DTLB_WAYS] =
- {
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF)
- },
- { XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES_LOG2),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, PAGESZ_LOG2_MIN),
- XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ARF)
- }
- };
-
- static inline char *way_type (int type)
- {
- return type ? "autorefill" : "non-autorefill";
- }
-
- void print_entry (struct way_config_t *way_info,
- unsigned int way,
- unsigned int index,
- unsigned int virtual,
- unsigned int translation)
- {
- char valid_chr;
- unsigned int va, pa, asid, ca;
-
- va = virtual & ~((1 << (way_info->pgsz_log2 + way_info->indicies_log2)) - 1);
- asid = virtual & ((1 << XCHAL_MMU_ASID_BITS) - 1);
- pa = translation & ~((1 << way_info->pgsz_log2) - 1);
- ca = translation & ((1 << XCHAL_MMU_CA_BITS) - 1);
- valid_chr = asid ? 'V' : 'I';
-
- /* Compute and incorporate the effect of the index bits on the
- * va. It's more useful for kernel debugging, since we always
- * want to know the effective va anyway. */
-
- va += index << way_info->pgsz_log2;
-
- printk ("\t[%d,%d] (%c) vpn 0x%.8x ppn 0x%.8x asid 0x%.2x am 0x%x\n",
- way, index, valid_chr, va, pa, asid, ca);
- }
-
- void print_itlb_entry (struct way_config_t *way_info, int way, int index)
- {
- print_entry (way_info, way, index,
- read_itlb_virtual (way + (index << way_info->pgsz_log2)),
- read_itlb_translation (way + (index << way_info->pgsz_log2)));
- }
-
- void print_dtlb_entry (struct way_config_t *way_info, int way, int index)
- {
- print_entry (way_info, way, index,
- read_dtlb_virtual (way + (index << way_info->pgsz_log2)),
- read_dtlb_translation (way + (index << way_info->pgsz_log2)));
- }
-
- void dump_itlb (void)
- {
- int way, index;
-
- printk ("\nITLB: ways = %d\n", XCHAL_ITLB_WAYS);
-
- for (way = 0; way < XCHAL_ITLB_WAYS; way++) {
- printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
- way, itlb[way].indicies,
- itlb[way].pgsz_log2, way_type(itlb[way].arf));
- for (index = 0; index < itlb[way].indicies; index++) {
- print_itlb_entry(&itlb[way], way, index);
- }
- }
- }
-
- void dump_dtlb (void)
- {
- int way, index;
-
- printk ("\nDTLB: ways = %d\n", XCHAL_DTLB_WAYS);
-
- for (way = 0; way < XCHAL_DTLB_WAYS; way++) {
- printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
- way, dtlb[way].indicies,
- dtlb[way].pgsz_log2, way_type(dtlb[way].arf));
- for (index = 0; index < dtlb[way].indicies; index++) {
- print_dtlb_entry(&dtlb[way], way, index);
- }
- }
- }
-
- void dump_tlbs (void)
- {
- dump_itlb();
- dump_dtlb();
- }
-
- #endif /* XT2000_MMU_DUMP == 1 */
--- 222,223 ----
|
|
From: <ma...@us...> - 2003-04-01 22:26:58
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv25932
Modified Files:
pgtable.h
Log Message:
Fix multihit kernel bug -- essentially adjust pte_none() and related code.
Also fix definitions of PTE entry format for swapped files, add descriptive
comments, and other sundry cleanup.
Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** pgtable.h 11 Mar 2003 19:17:00 -0000 1.10
--- pgtable.h 1 Apr 2003 22:26:53 -0000 1.11
***************
*** 11,16 ****
* for more details.
*
! * Copyright (C) 2001 Tensilica Inc.
! * Authors: Marc Gauthier
* Joe Taylor <jo...@te..., jo...@ya...>
*/
--- 11,16 ----
* for more details.
*
! * Copyright (C) 2001 - 2003 Tensilica Inc.
! * Authors: Marc Gauthier <ma...@te...> <ma...@al...>
* Joe Taylor <jo...@te..., jo...@ya...>
*/
***************
*** 23,26 ****
--- 23,27 ----
#ifndef _LANGUAGE_ASSEMBLY
+ #include <linux/sched.h>
#include <linux/linkage.h>
#include <linux/config.h>
***************
*** 35,46 ****
#if XTENSA_CACHE_ALIAS
! /* We provide our own get_unmapped_area to avoid cache alias issue */
#define HAVE_ARCH_UNMAPPED_AREA
#define PG_mapped PG_arch_1
! /* this is a mask of the naughty bits that can cause cache aliasing
! * problems. Because xtensa has a configurable cache size we have to
! * get funky.... Start with 0xffff_ffff and then mask off everything
! * else that is not a problem...
*/
#define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
--- 36,46 ----
#if XTENSA_CACHE_ALIAS
! /* We provide our own get_unmapped_area to avoid cache alias issues */
#define HAVE_ARCH_UNMAPPED_AREA
#define PG_mapped PG_arch_1
! /* This is a mask of the bits that can cause cache aliasing problems.
! * Because Xtensa has a configurable cache size, we use
! * configuration information to compute the mask.
*/
#define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
***************
*** 50,55 ****
! /* Only if the dcache is writeback do we still need to flush at
! * times. Cache aliasing is not allowed (yet) and not supported (yet).
*/
--- 50,55 ----
!
! /* If the dcache is writeback or we have cache aliasing, may need to flush.
*/
***************
*** 83,86 ****
--- 83,87 ----
+
/* 19feb2003 -- jn
* enabling dcache aliasing
***************
*** 100,107 ****
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
! /* Basically we have the same two-level (which is the logical three
! * level Linux page table layout folded) page tables as the i386. Use
! * the first min-wired way for mapping page-table pages. Page
! * coloring requires a second min-wired way.
*/
--- 101,107 ----
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
!
! /* Use the first min-wired way for mapping page-table pages.
! * Page coloring requires a second min-wired way.
*/
***************
*** 125,134 ****
! /* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT 22
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
! /* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT 22
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
--- 125,160 ----
! /*
! * The Xtensa architecture port of Linux uses essentially the same
! * two-level page tables as the i386, i.e. the logical three-level
! * Linux page table layout folded. That is, for each task's memory space:
! *
! * the PGD table (page directory), ie. 3rd-level page table,
! * is one page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
! * (are ptrs to PMD tables in arch's where PMDs are not folded).
! *
! * For a given task, the pointer to the PGD table is:
! * (t->mm ? t->mm : t->active_mm)->pgd
! * where t is (struct task_struct *) (eg. current()).
! *
! * the PMD tables (page middle-directory), ie. 2nd-level page tables,
! * are absent (folded, PTRS_PER_PMD == 1).
! *
! * the PTE tables (page table entry), ie. 1st-level page tables,
! * are one page (4 kB) of 1024 (PTRS_PER_PTE) PTEs;
! * special PTE tables include:
! * - invalid_pte_table (pointed to by PMD table, for absent mappings)
! *
! * individual pages are 4 kB;
! * special pages include:
! * - empty_zero_page
! */
!
! /* PMD_SHIFT determines the v.m. size a PMD table *entry* can map */
#define PMD_SHIFT 22
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
! /* PGDIR_SHIFT determines the v.m. size a PGD table *entry* can map */
#define PGDIR_SHIFT 22
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
***************
*** 142,146 ****
#define PTRS_PER_PGD 1024
#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
! #define FIRST_USER_PGD_NR 0
/* 27feb2003 -- jn
--- 168,172 ----
#define PTRS_PER_PGD 1024
#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
! #define FIRST_USER_PGD_NR 0 /* task VM starts at address zero */
/* 27feb2003 -- jn
***************
*** 154,169 ****
#if (XTENSA_CACHE_ALIAS)
! #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
! #define XTENSA_ALIAS_RESERVE_START 0xC0010000
! #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
#else
! #define VMALLOC_START 0xC0010000
#endif
! #define VMALLOC_VMADDR(x) ((unsigned long)(x))
! #define VMALLOC_END 0xC7FF0000
! /* Xtensa Linux config PTE layout:
* 31-12: PPN
* 11-6: software:
--- 180,211 ----
#if (XTENSA_CACHE_ALIAS)
! #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
! #define XTENSA_ALIAS_RESERVE_START 0xC0010000
! #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
#else
! #define VMALLOC_START 0xC0010000
#endif
! #define VMALLOC_VMADDR(x) ((unsigned long)(x))
! #define VMALLOC_END 0xC7FF0000
!
! /* More assumptions: */
! #if (XCHAL_MMU_RINGS != 4)
! #error Linux build assumes 4 ring levels.
! #endif
! #if (XCHAL_MMU_RING_BITS != 2)
! #error We assume exactly two bits for RING.
! #endif
! #if (XCHAL_MMU_CA_BITS != 4)
! #error We assume exactly four bits for CA.
! #endif
! #if (XCHAL_MMU_SR_BITS != 0)
! #error We have no room for SR bits.
! #endif
!
!
! /* Xtensa Linux config PTE layout (when present):
* 31-12: PPN
* 11-6: software:
***************
*** 184,205 ****
* process write to the page, this keeps a mod bit via the hardware
* dirty bit.
*/
! #if (XCHAL_MMU_RINGS != 4)
! #error Linux build assumes 4 ring levels.
! #endif
! #if (XCHAL_MMU_RING_BITS != 2)
! #error We assume exactly two bits for RING.
! #endif
! #if (XCHAL_MMU_CA_BITS != 4)
! #error We assume exactly four bits for CA.
! #endif
! #if (XCHAL_MMU_SR_BITS != 0)
! #error We have no room for SR bits.
! #endif
! #define GLOBAL_RING 3 /* global ring level */
! #define USER_RING 1 /* user ring level */
! #define KERNEL_RING 0 /* kernel ring level */
#define _PAGE_GLOBAL (GLOBAL_RING<<4) /* ring: global access (ring=3) */
--- 226,249 ----
* process write to the page, this keeps a mod bit via the hardware
* dirty bit.
+ *
+ * See further below for PTE layout for swapped-out pages.
*/
! #define GLOBAL_RING 3 /* global ring level (user-level) */
! #define USER_RING 1 /* user ring level */
! #define KERNEL_RING 0 /* kernel ring level (also global) */
! #define _PAGE_VALID (1<<0) /* ca: page is accessible
! (todo: replace with CA!=invalid) */
! #define _PAGE_SILENT_READ (1<<0) /* ca: (synonym)*/
! #define _PAGE_DIRTY (1<<1) /* ca: page is writable
! (because store attempted, so is "dirty") */
! #define _PAGE_SILENT_WRITE (1<<1) /* ca: (synonym) */
! /* None of these cache modes include MP coherency: */
! #define _CACHE_BYPASS (0<<2) /* ca: bypass cache non-speculative */
! #define _CACHE_CACHABLE_NONCOHERENT (1<<2) /* ca: cachable speculative */
! #define _CACHE_UNCACHED (2<<2) /* ca: uncached speculative */
! #define _CACHE_CACHABLE_SPECIAL (3<<2) /* ca: special (isolate, no execute, ...) */
! #define _CACHE_MASK (15<<0) /* ca: all CA bits */
#define _PAGE_GLOBAL (GLOBAL_RING<<4) /* ring: global access (ring=3) */
***************
*** 207,233 ****
#define _PAGE_USER (USER_RING<<4) /* ring: user access (ring=1) */
#define _PAGE_KERNEL (KERNEL_RING<<4) /* ring: kernel access (ring=0) */
! #define _PAGE_PRESENT (1<<6) /* software: (have translation / page not swapped out?) */
! #define _PAGE_READ (1<<7) /* software: page readable */
! #define _PAGE_WRITE (1<<8) /* software: page writable */
! #define _PAGE_ACCESSED (1<<9) /* software: page accessed (read) */
! #define _PAGE_MODIFIED (1<<10) /* software: page modified (written/dirty) */
!
! #define _PAGE_VALID (1<<0) /* ca: !! replaced with CA!=invalid */
! #define _PAGE_SILENT_READ (1<<0) /* ca: !! synonym */
! #define _PAGE_DIRTY (1<<1) /* ca: !! replaced with CA!=readonly (MIPS dirty bit) */
! #define _PAGE_SILENT_WRITE (1<<1) /* ca: ... */
! #define _CACHE_BYPASS (0<<2) /* ca: bypass cache non-speculative (no MP coherency) */
! #define _CACHE_CACHABLE_NONCOHERENT (1<<2) /* ca: cachable speculative (no MP coherency) */
! #define _CACHE_UNCACHED (2<<2) /* ca: uncached speculative (no MP coherency) */
! #define _CACHE_CACHABLE_SPECIAL (3<<2) /* ca: special (isolate, no execute, ...) (no MP coherency) */
! #define _CACHE_MASK (15<<0) /* ca: all CA bits */
!
! /*#define _CACHE_CACHABLE_NO_WA (0<<0)*/ /* R4600 only */
! /*#define _CACHE_CACHABLE_WA (1<<0)*/ /* R4600 only */
! /*#define _CACHE_CACHABLE_CE (4<<0)*/ /* R4[04]00 only */
! /*#define _CACHE_CACHABLE_COW (5<<0)*/ /* R4[04]00 only */
! /*#define _CACHE_CACHABLE_CUW (6<<0)*/ /* R4[04]00 only */
! /*#define _CACHE_CACHABLE_ACCELERATED (7<<0)*/ /* R10000 only */
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
--- 251,261 ----
#define _PAGE_USER (USER_RING<<4) /* ring: user access (ring=1) */
#define _PAGE_KERNEL (KERNEL_RING<<4) /* ring: kernel access (ring=0) */
+ #define _PAGE_RING_MASK (3<<4) /* ring bits */
! #define _PAGE_PRESENT (1<<6) /* software: page not swapped out nor "none" */
! #define _PAGE_READ (1<<7) /* software: page readable */
! #define _PAGE_WRITE (1<<8) /* software: page writable */
! #define _PAGE_ACCESSED (1<<9) /* software: page accessed (read) */
! #define _PAGE_MODIFIED (1<<10) /* software: page modified (written/dirty) */
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
***************
*** 258,262 ****
* read. Also, write permissions may imply read permissions.
* What follows is the closest we can get by reasonable means..
! * See linux/mm/mmap.c for protection_map[] array that uses these definitions. */
#define __P000 PAGE_NONE /* private --- */
#define __P001 PAGE_READONLY /* private --r */
--- 286,291 ----
* read. Also, write permissions may imply read permissions.
* What follows is the closest we can get by reasonable means..
! * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
! */
#define __P000 PAGE_NONE /* private --- */
#define __P001 PAGE_READONLY /* private --r */
***************
*** 280,291 ****
#define pte_ERROR(e) \
! printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
! printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
! printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
/*
! * BAD_PAGETABLE is used when we need a bogus page-table, while
* BAD_PAGE is used for a bogus page.
*
--- 309,320 ----
#define pte_ERROR(e) \
! printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
! printk("%s:%d: bad pmd entry %08lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
! printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
/*
! * BAD_PAGETABLE is used when we need a bogus (PTE) page-table, while
* BAD_PAGE is used for a bogus page.
*
***************
*** 319,324 ****
extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
! extern pgd_t invalid_pte_table[PAGE_SIZE/sizeof(pgd_t)];
! extern pte_t exception_pte_table[PAGE_SIZE/sizeof(pte_t)];
/* to find an entry in a page-table */
--- 348,352 ----
extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
! extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pgd_t)];
/* to find an entry in a page-table */
***************
*** 342,347 ****
}
! extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
! extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
/* Certain architectures need to do special things when pte's
--- 370,400 ----
}
! /*
! * Notes:
! * - Conditions pte_none() and pte_valid() are mutually exclusive.
! * - Conditions pte_none() and pte_present() are mutually exclusive.
! * - PTEs reported as neither pte_none() nor pte_present() contain information
! * about swapped out pages; the format of these is described further below
! * with the SWP_xxx() macro definitions.
! * - PTEs reported as pte_valid() are always pte_present(), but the reverse
! * is not always true.
! * - pte_clear() causes a PTE entry to satisfy the pte_none() condition.
! *
! * Certain virtual addresses must have specific non-zero ring levels.
! * Which means that a PTE cannot be all zeroes (at least not for
! * any virtual address that might ever be accessible by a user task)
! * to indicate the pte_none() condition. So we mask out the ring
! * in the pte_none() comparison.
! *
! * XTFIXME: we might get a slight optimization on this by assuming we
! * always use _PAGE_USER for pte_none() entries (which appears to be the
! * case currently), thus comparing the PTE with _PAGE_USER rather
! * than masking out ring bits then comparing to zero.
! */
! extern inline void set_pte(pte_t *ptep, pte_t pteval);
! extern inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PAGE_RING_MASK) == 0; }
! extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
! extern inline int pte_valid(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
! extern inline void pte_clear(pte_t *ptep) { set_pte(ptep, __pte(_PAGE_USER)); }
/* Certain architectures need to do special things when pte's
***************
*** 362,369 ****
}
- extern inline void pte_clear(pte_t *ptep)
- {
- set_pte(ptep, __pte(0));
- }
/*
--- 415,418 ----
***************
*** 393,396 ****
--- 442,446 ----
}
+
/*
* The "pgd_xxx()" functions here are trivial for a folded two-level
***************
*** 403,406 ****
--- 453,457 ----
extern inline void pgd_clear(pgd_t *pgdp) { }
+
/*
* Permanent address of a page.
***************
*** 409,416 ****
--- 460,469 ----
#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
+
/*
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
+
extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
***************
*** 474,477 ****
--- 527,531 ----
}
+
/*
* Conversion functions: convert a page and protection to a page entry,
***************
*** 503,510 ****
}
! #define page_pte(page) page_pte_prot(page, __pgprot(0))
/* to find an entry in a kernel page-table-directory */
! #define pgd_offset_k(address) pgd_offset(&init_mm, address)
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
--- 557,564 ----
}
! #define page_pte(page) page_pte_prot(page, __pgprot(0))
/* to find an entry in a kernel page-table-directory */
! #define pgd_offset_k(address) pgd_offset(&init_mm, address)
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
***************
*** 603,609 ****
extern void paging_init(void);
! #define SWP_TYPE(x) (((x).val >> 1) & 0x3f)
! #define SWP_OFFSET(x) ((x).val >> 8)
! #define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define swp_entry_to_pte(x) ((pte_t) { (x).val })
--- 657,702 ----
extern void paging_init(void);
! /*
! * Define swap file entries, which are PTEs for swapped-out pages.
! *
! * Background:
! * Each PTE in a process VM's page table is either:
! * "present" -- valid and not swapped out, protection bits are meaningful;
! * "not present" -- which further subdivides in these two cases:
! * "none" -- no mapping at all; identified by pte_none(), set by pte_clear();
! * "swapped out" -- the page is swapped out, and the SWP macros below
! * are used to store swap file info in the PTE itself.
! *
! * In the Xtensa processor MMU, any PTE entries in user space (or anywhere
! * in virtual memory that can map differently across address spaces)
! * must have a correct ring value that represents the RASID field that
! * is changed when switching address spaces. Eg. such PTE entries cannot
! * be set to ring zero, because that can cause a (global) kernel ASID
! * entry to be created in the TLBs (even with invalid cache attribute),
! * potentially causing a multihit exception when going back to another
! * address space that mapped the same virtual address at another ring.
! *
! * SO: we avoid using ring bits (_PAGE_RING_MASK) in "not present" PTEs.
! * We also avoid using the _PAGE_VALID and _PAGE_PRESENT bits which must
! * be zero for non-present pages.
! *
! * We end up with the following available bits: 1..3 and 7..31.
! * We don't bother with 1..3 for now (we can use them later if needed),
! * and chose to allocate 6 bits for SWP_TYPE and the remaining 19 bits
! * for SWP_OFFSET. At least 5 bits are needed for SWP_TYPE, because it
! * is currently implemented as an index into swap_info[MAX_SWAPFILES]
! * and MAX_SWAPFILES is currently defined as 32 in <linux/swap.h>.
! * However, for some reason all other architectures in the 2.4 kernel
! * reserve either 6, 7, or 8 bits so I'll not detract from that for now. :)
! * SWP_OFFSET is an offset into the swap file in page-size units, so
! * with 4 kB pages, 19 bits supports a maximum swap file size of 2 GB.
! *
! * XTFIXME: 2 GB isn't very big. Other bits can be used to allow
! * larger swap sizes. In the meantime, it appears relatively easy to get
! * around the 2 GB limitation by simply using multiple swap files.
! */
! #define SWP_TYPE(x) (((x).val >> 7) & 0x3f)
! #define SWP_OFFSET(x) ((x).val >> 13)
! #define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 7) | ((offset) << 13) })
#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define swp_entry_to_pte(x) ((pte_t) { (x).val })
***************
*** 633,637 ****
unsigned long tmp;
__asm__ __volatile__ (" rsr %0, "XTSTR(RASID)"\n\t"
- " isync\n"
: "=a" (tmp));
return tmp;
--- 726,729 ----
***************
*** 714,718 ****
unsigned long tmp;
__asm__ __volatile__("rsr %0, "XTSTR(PTEVADDR)"\n\t"
- "dsync\n"
: "=a" (tmp));
return tmp;
--- 806,809 ----
***************
*** 836,844 ****
/* The kernel (in mm/memory.c) often invokes this macro when a page
* previously wasn't mapped. In handle_2nd_level_miss() when no page
! * is mapped, we map the exception_pte_table into the Page Table to
* generate another exception that exposes the type of access. After
* mapping in the appropriate page (often by calling the kernel's
* handle_mm_fault()), we need to remove the mapping of
! * exception_pte_table from the Page Table. This macro does this
* function. The 2nd-level miss handler will later fill in the
* correct mapping. */
--- 927,935 ----
/* The kernel (in mm/memory.c) often invokes this macro when a page
* previously wasn't mapped. In handle_2nd_level_miss() when no page
! * is mapped, we map the invalid_pte_table into the Page Table to
* generate another exception that exposes the type of access. After
* mapping in the appropriate page (often by calling the kernel's
* handle_mm_fault()), we need to remove the mapping of
! * invalid_pte_table from the Page Table. This macro does this
* function. The 2nd-level miss handler will later fill in the
* correct mapping. */
|
|
From: <ma...@us...> - 2003-04-01 22:10:48
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm In directory sc8-pr-cvs1:/tmp/cvs-serv24339 Modified Files: loadmmu.c Log Message: Remove warnings. Index: loadmmu.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/loadmmu.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** loadmmu.c 1 Apr 2003 20:30:54 -0000 1.2 --- loadmmu.c 1 Apr 2003 22:10:31 -0000 1.3 *************** *** 87,93 **** XCHAL_ICACHE_SIZE >> 10, 1 << XCHAL_ICACHE_LINEWIDTH); ! _dma_cache_wback_inv = xt_panic; ! _dma_cache_wback = xt_panic; ! _dma_cache_inv = xt_panic; flush_tlb_all(); --- 87,93 ---- XCHAL_ICACHE_SIZE >> 10, 1 << XCHAL_ICACHE_LINEWIDTH); ! (void(*)(void))_dma_cache_wback_inv = xt_panic; ! (void(*)(void))_dma_cache_wback = xt_panic; ! (void(*)(void))_dma_cache_inv = xt_panic; flush_tlb_all(); |
|
From: <ma...@us...> - 2003-04-01 22:08:28
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv23065
Modified Files:
setup.c
Log Message:
Remove a warning.
Index: setup.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/setup.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** setup.c 28 Feb 2003 01:53:09 -0000 1.9
--- setup.c 1 Apr 2003 22:08:12 -0000 1.10
***************
*** 253,257 ****
retpc = current_retpc; /* and current return address */
for( i = 0; i < MAX_TRACEBACK; i++ ) {
! if( ((unsigned)sp & 3) != 0 || sp <= prevsp || sp > __KSTK_TOS(current) ) {
printk( " (stack pointer out of range or unaligned)\n" );
break;
--- 253,258 ----
retpc = current_retpc; /* and current return address */
for( i = 0; i < MAX_TRACEBACK; i++ ) {
! if( ((unsigned)sp & 3) != 0
! || sp <= prevsp || sp > (unsigned*)__KSTK_TOS(current) ) {
printk( " (stack pointer out of range or unaligned)\n" );
break;
|
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From: <ma...@us...> - 2003-04-01 21:12:55
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/platform-xt2000 In directory sc8-pr-cvs1:/tmp/cvs-serv23364 Modified Files: machvec.h Log Message: Add missing XT2000-specific prototype to get rid of a warning. Index: machvec.h =================================================================== RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/platform-xt2000/machvec.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** machvec.h 28 Aug 2002 16:11:31 -0000 1.1.1.1 --- machvec.h 1 Apr 2003 20:55:26 -0000 1.2 *************** *** 6,15 **** * for more details. * ! * Copyright (C) 2001 Tensilica Inc. */ /* ! * This file defines the platform-dependent functions, that are ! * provided by the xt2000 port */ --- 6,15 ---- * for more details. * ! * Copyright (C) 2001 - 2003 Tensilica Inc. */ /* ! * This file defines the platform-dependent functions ! * provided by the XT2000 port. */ *************** *** 20,24 **** extern void xt2000_setup (char **); ! extern int xt2000_pci_map_irq (struct pci_dev*, u8, u8); /* generic functions (must be implemented) */ --- 20,25 ---- extern void xt2000_setup (char **); ! extern int xt2000_pci_map_irq (struct pci_dev*, u8, u8); ! extern void xt2000_pci_fixup (void); /* generic functions (must be implemented) */ |
|
From: <ma...@us...> - 2003-04-01 20:31:00
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm In directory sc8-pr-cvs1:/tmp/cvs-serv13455 Modified Files: loadmmu.c Log Message: Trivial performance tweak. Index: loadmmu.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/loadmmu.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** loadmmu.c 28 Aug 2002 16:10:14 -0000 1.1.1.1 --- loadmmu.c 1 Apr 2003 20:30:54 -0000 1.2 *************** *** 39,45 **** "s32i %2, %1, 20\n\t" "s32i %2, %1, 24\n\t" "s32i %2, %1, 28\n\t" "addi %1, %1, 32\n\t" - "addi %0, %0, 32\n\t" "bltz %0, 1b\n" : "=r" (bytes), "=r" (page) --- 39,45 ---- "s32i %2, %1, 20\n\t" "s32i %2, %1, 24\n\t" + "addi %0, %0, 32\n\t" "s32i %2, %1, 28\n\t" "addi %1, %1, 32\n\t" "bltz %0, 1b\n" : "=r" (bytes), "=r" (page) *************** *** 69,77 **** "s32i %3, %1, 16\n\t" "s32i %4, %1, 20\n\t" "s32i %5, %1, 24\n\t" "s32i %6, %1, 28\n\t" "addi %1, %1, 32\n\t" - "addi %2, %2, 32\n\t" - "addi %0, %0, 32\n\t" "bltz %0, 1b\n" : "+r" (bytes), "+r" (to), "+r" (from), --- 69,77 ---- "s32i %3, %1, 16\n\t" "s32i %4, %1, 20\n\t" + "addi %0, %0, 32\n\t" "s32i %5, %1, 24\n\t" + "addi %2, %2, 32\n\t" "s32i %6, %1, 28\n\t" "addi %1, %1, 32\n\t" "bltz %0, 1b\n" : "+r" (bytes), "+r" (to), "+r" (from), |
|
From: <ma...@us...> - 2003-04-01 19:59:21
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv31643
Modified Files:
mmu_context.h page.h
Log Message:
Trivial comment fixes.
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/mmu_context.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** mmu_context.h 11 Mar 2003 19:17:00 -0000 1.5
--- mmu_context.h 1 Apr 2003 19:59:17 -0000 1.6
***************
*** 13,17 ****
* Copyright (C) 2001 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
! * Marc Gauthier
*/
--- 13,17 ----
* Copyright (C) 2001 Tensilica Inc.
* Authors: Joe Taylor <jo...@te..., jo...@ya...>
! * Marc Gauthier <ma...@te...> <ma...@al...>
*/
***************
*** 52,56 ****
value. mm->context has the same meaning. When it comes time to
write the asid_cache or mm->context values to the RASID special
! register, we first shift the value left by 8, the insert the value.
ASID[0] always contains the kernel's asid value, and we reserve
three other asid values that we never assign to user tasks. */
--- 52,56 ----
value. mm->context has the same meaning. When it comes time to
write the asid_cache or mm->context values to the RASID special
! register, we first shift the value left by 8, then insert the value.
ASID[0] always contains the kernel's asid value, and we reserve
three other asid values that we never assign to user tasks. */
Index: page.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/page.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** page.h 28 Feb 2003 01:53:10 -0000 1.4
--- page.h 1 Apr 2003 19:59:17 -0000 1.5
***************
*** 66,72 ****
* These are used to make use of C type-checking..
*/
! typedef struct { unsigned long pte; } pte_t;
! typedef struct { unsigned long pmd; } pmd_t;
! typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
--- 66,72 ----
* These are used to make use of C type-checking..
*/
! typedef struct { unsigned long pte; } pte_t; /* page table entry */
! typedef struct { unsigned long pmd; } pmd_t; /* PMD table entry */
! typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
typedef struct { unsigned long pgprot; } pgprot_t;
|
|
From: <ma...@us...> - 2003-04-01 19:58:10
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv30921
Modified Files:
dma.h
Log Message:
Fix MAX_DMA_ADDRESS macro, and add relevant comments.
Index: dma.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/dma.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** dma.h 28 Aug 2002 16:11:31 -0000 1.1.1.1
--- dma.h 1 Apr 2003 19:58:06 -0000 1.2
***************
*** 10,27 ****
* for more details.
*
! * Copyright (C) 2001 Tensilica Inc.
*/
#include <linux/config.h>
#include <asm/io.h> /* need byte IO */
! #define MAX_DMA_CHANNELS 8
- /* The maximum address that we can perform a DMA transfer to on this platform */
- /* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
- occurrence should be flagged as an error. */
- /* But... */
- /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
- #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
--- 10,55 ----
* for more details.
*
! * Copyright (C) 2003 Tensilica Inc.
*/
#include <linux/config.h>
#include <asm/io.h> /* need byte IO */
+ #include <xtensa/config/core.h>
! /*
! * This is only to be defined if we have PC-like DMA.
! * By default this is not true on an Xtensa processor,
! * however on boards with a PCI bus, such functionality
! * might be emulated externally (eg. on the XT2000?
! * XTFIXME: verify).
! *
! * NOTE: there still exists driver code that assumes
! * this is defined, eg. drivers/sound/soundcard.c (as of 2.4).
! */
! #define MAX_DMA_CHANNELS 8
!
! /*
! * The maximum virtual address to which DMA transfers
! * can be performed on this platform.
! *
! * NOTE: This is board (platform) specific, not processor-specific!
! *
! * NOTE: This assumes DMA transfers can only be performed on
! * the section of physical memory contiguously mapped in virtual
! * space for the kernel. For the Xtensa architecture, this
! * means the maximum possible size of this DMA area is
! * the size of the statically mapped kernel segment
! * (XCHAL_KSEG_{CACHED,BYPASS}_SIZE), ie. 128 MB.
! *
! * NOTE: When the entire KSEG area is DMA capable, we substract
! * one from the max address so that the virt_to_phys() macro
! * works correctly on the address (otherwise the address
! * enters another area, and virt_to_phys() may not return
! * the value desired).
! *
! * XTFIXME: need more appropriate values for XT2000 and ISS.
! */
! #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KSEG_CACHED_SIZE - 1)
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
|
|
From: <joe...@us...> - 2003-03-31 23:31:42
|
Update of /cvsroot/xtensa/linux/arch/xtensa In directory sc8-pr-cvs1:/tmp/cvs-serv7666/arch/xtensa Added Files: defconfig Log Message: Provide some default kernel-configuration settings. --- NEW FILE: defconfig --- # # Automatically generated by make menuconfig: don't edit # CONFIG_XTENSA=y CONFIG_UID16=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # # Code maturity level options # CONFIG_EXPERIMENTAL=y # # Loadable module support # CONFIG_MODULES=y # CONFIG_MODVERSIONS is not set CONFIG_KMOD=y # # Platform dependent support # CONFIG_XTENSA_CONFIG_LINUX_BE=y # CONFIG_XTENSA_CONFIG_LINUX_LE is not set # CONFIG_XTENSA_CONFIG_LINUX_TEST is not set # CONFIG_XTENSA_PLATFORM_ISS is not set CONFIG_XTENSA_PLATFORM_XT2000=y CONFIG_XTENSA_CALIBRATE=y # CONFIG_SMP is not set # CONFIG_IEEEFPU_EMULATION is not set # # General setup # # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_SBUS is not set # CONFIG_MCA is not set CONFIG_PCI=y CONFIG_NET=y CONFIG_SYSCTL=y CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_KCORE_ELF=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS0,38400 root=/dev/nfs ip=bootp" # CONFIG_PCI_NAMES is not set # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Plug and Play configuration # # CONFIG_PNP is not set # CONFIG_ISAPNP is not set # # Block devices # # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_INITRD=y # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # CONFIG_BLK_DEV_MD is not set # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID5 is not set # CONFIG_MD_MULTIPATH is not set # CONFIG_BLK_DEV_LVM is not set # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set # CONFIG_NETLINK_DEV is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set # CONFIG_FILTER is not set CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set # # IP: Netfilter Configuration # # CONFIG_IP_NF_CONNTRACK is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_COMPAT_IPCHAINS is not set # CONFIG_IP_NF_COMPAT_IPFWADM is not set # CONFIG_IPV6 is not set # CONFIG_KHTTPD is not set # CONFIG_ATM is not set # CONFIG_VLAN_8021Q is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set # CONFIG_NET_HW_FLOWCONTROL is not set # # QoS and/or fair queueing # # CONFIG_NET_SCHED is not set # # ATA/IDE/MFM/RLL support # # CONFIG_IDE is not set # CONFIG_BLK_DEV_IDE_MODES is not set # CONFIG_BLK_DEV_HD is not set # # SCSI support # # CONFIG_SCSI is not set # # IEEE 1394 (FireWire) support (EXPERIMENTAL) # # CONFIG_IEEE1394 is not set # # I2O device support # # CONFIG_I2O is not set # CONFIG_I2O_PCI is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # # Network device support # CONFIG_NETDEVICES=y # # ARCnet devices # # CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y CONFIG_XTENSA_PLATFORM_XT2000_SONIC=y # CONFIG_SUNLANCE is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNBMAC is not set # CONFIG_SUNQE is not set # CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set # CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_MYRI_SBUS is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PLIP is not set CONFIG_PPP=m CONFIG_PPP_MULTILINK=y # CONFIG_PPP_FILTER is not set CONFIG_PPP_ASYNC=m # CONFIG_PPP_SYNC_TTY is not set CONFIG_PPP_DEFLATE=m # CONFIG_PPP_BSDCOMP is not set CONFIG_PPPOE=m # CONFIG_SLIP is not set # # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set # # Token Ring devices # # CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # # Wan interfaces # # CONFIG_WAN is not set # # Amateur Radio support # # CONFIG_HAMRADIO is not set # # IrDA (infrared) support # # CONFIG_IRDA is not set # # ISDN subsystem # # CONFIG_ISDN is not set # # Console drivers # # # Frame-buffer support # # CONFIG_FB is not set # # Input core support # # CONFIG_INPUT is not set # CONFIG_INPUT_KEYBDEV is not set # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # # Character devices # CONFIG_VT=y # CONFIG_VT_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 # # I2C support # # CONFIG_I2C is not set # # Mice # # CONFIG_BUSMOUSE is not set # CONFIG_MOUSE is not set # # Joysticks # # CONFIG_INPUT_GAMEPORT is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # File systems # # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set CONFIG_AUTOFS4_FS=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set CONFIG_EXT3_FS=m CONFIG_JBD=m # CONFIG_JBD_DEBUG is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m CONFIG_TMPFS=y CONFIG_RAMFS=m # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set CONFIG_EXT2_FS=m # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set # # Network File Systems # # CONFIG_CODA_FS is not set # CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y CONFIG_NFSD=m # CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y CONFIG_LOCKD=y CONFIG_SMB_FS=m # CONFIG_SMB_NLS_DEFAULT is not set # CONFIG_NCP_FS is not set # CONFIG_NCPFS_PACKET_SIGNING is not set # CONFIG_NCPFS_IOCTL_LOCKING is not set # CONFIG_NCPFS_STRONG is not set # CONFIG_NCPFS_NFS_NS is not set # CONFIG_NCPFS_OS2_NS is not set # CONFIG_NCPFS_SMALLDOS is not set # CONFIG_NCPFS_NLS is not set # CONFIG_NCPFS_EXTRAS is not set # CONFIG_ZISOFS_FS is not set CONFIG_ZLIB_FS_INFLATE=m # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y CONFIG_SMB_NLS=y CONFIG_NLS=y # # Native Language Support # CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # # Sound # # CONFIG_SOUND is not set # # USB support # # CONFIG_USB is not set # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set # CONFIG_USB_OHCI is not set # CONFIG_USB_AUDIO is not set # CONFIG_USB_BLUETOOTH is not set # CONFIG_USB_STORAGE is not set # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_HP8200e is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_DC2XX is not set # CONFIG_USB_MDC800 is not set # CONFIG_USB_SCANNER is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USB_HPUSBSCSI is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_CATC is not set # CONFIG_USB_CDCETHER is not set # CONFIG_USB_USBNET is not set # CONFIG_USB_USS720 is not set # # USB Serial Converter support # # CONFIG_USB_SERIAL is not set # CONFIG_USB_SERIAL_GENERIC is not set # CONFIG_USB_SERIAL_BELKIN is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set # CONFIG_USB_SERIAL_EMPEG is not set # CONFIG_USB_SERIAL_FTDI_SIO is not set # CONFIG_USB_SERIAL_VISOR is not set # CONFIG_USB_SERIAL_IR is not set # CONFIG_USB_SERIAL_EDGEPORT is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set # CONFIG_USB_SERIAL_KEYSPAN is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_RIO500 is not set # # Bluetooth support # # CONFIG_BLUEZ is not set # # Kernel hacking # # CONFIG_MAGIC_SYSRQ is not set # CONFIG_KGDB is not set |
|
From: <joe...@us...> - 2003-03-31 23:30:03
|
Update of /cvsroot/xtensa/linux/arch/xtensa/mm
In directory sc8-pr-cvs1:/tmp/cvs-serv7038/arch/xtensa/mm
Modified Files:
mmu.c
Log Message:
Remove deprecated i[id]tlba instructions.
Index: mmu.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/mm/mmu.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** mmu.c 11 Mar 2003 21:14:17 -0000 1.9
--- mmu.c 31 Mar 2003 23:30:00 -0000 1.10
***************
*** 55,66 ****
unsigned long flags;
save_and_cli (flags);
- #if 1
- __asm__ __volatile__ ("iitlba\n\t"
- "idtlba\n\t"
- "isync\n\t"); /* isync includes dsync */
- #else
xtensa_flush_all_itlb();
xtensa_flush_all_dtlb();
- #endif
restore_flags (flags);
}
--- 55,60 ----
|
|
From: <ma...@us...> - 2003-03-29 00:08:11
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv5529 Modified Files: handlers.S Log Message: Debug exception handler must examine EPS[DEBUGLEVEL], not simply PS. Index: handlers.S =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/handlers.S,v retrieving revision 1.15 retrieving revision 1.16 diff -C2 -d -r1.15 -r1.16 *** handlers.S 20 Mar 2003 20:45:37 -0000 1.15 --- handlers.S 29 Mar 2003 00:08:06 -0000 1.16 *************** *** 2845,2849 **** handle_debug: ! rsr a0, PS // Check if in user or kernel mode wsr a2, DEPC // preserve a2 so we can use it bbsi.l a0, PS_EXCM_SHIFT, 3f // jump if in exception mode --- 2845,2849 ---- handle_debug: ! rsr a0, EPS + XCHAL_DEBUGLEVEL // Check exception vs. user vs. kernel mode wsr a2, DEPC // preserve a2 so we can use it bbsi.l a0, PS_EXCM_SHIFT, 3f // jump if in exception mode |
|
From: <ahe...@us...> - 2003-03-28 00:29:44
|
Update of /cvsroot/xtensa/linux/drivers/mtd/maps
In directory sc8-pr-cvs1:/tmp/cvs-serv32434/drivers/mtd/maps
Modified Files:
Config.in Makefile
Added Files:
xtensa_xt2000.c
Log Message:
Added new mapping file for xtensa xt2000 board.
--- NEW FILE: xtensa_xt2000.c ---
/*
* $Id: xtensa_xt2000.c,v 1.1 2003/03/28 00:29:41 ahennessy Exp $
*
* Mapping of the Tensilica XT2000 board with Intel Strata flashes.
*
* Based on cstm_mips_ixx.c
*
* Copyright 2003 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/config.h>
#include <xtensa/xt2000.h>
#define WINDOW_ADDR XTBOARD_FLASH_VADDR
#define WINDOW_SIZE 0x2000000
#define WINDOW_BUSWIDTH 4
extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
__u8 xtensa_xt2000_read8(struct map_info *map, unsigned long ofs)
{
return *(__u8 *)(map->map_priv_1 + ofs);
}
__u16 xtensa_xt2000_read16(struct map_info *map, unsigned long ofs)
{
return *(__u16 *)(map->map_priv_1 + ofs);
}
__u32 xtensa_xt2000_read32(struct map_info *map, unsigned long ofs)
{
return *(__u32 *)(map->map_priv_1 + ofs);
}
void xtensa_xt2000_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
{
memcpy_fromio(to, map->map_priv_1 + from, len);
}
void xtensa_xt2000_write8(struct map_info *map, __u8 d, unsigned long adr)
{
*(__u8 *)(map->map_priv_1 + adr) = d;
}
void xtensa_xt2000_write16(struct map_info *map, __u16 d, unsigned long adr)
{
*(__u16 *)(map->map_priv_1 + adr) = d;
}
void xtensa_xt2000_write32(struct map_info *map, __u32 d, unsigned long adr)
{
*(__u32 *)(map->map_priv_1 + adr) = d;
}
void xtensa_xt2000_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
memcpy_toio(map->map_priv_1 + to, from, len);
}
const struct map_info basic_xtensa_xt2000_map = {
name: NULL,
size: 0,
buswidth: 0,
read8: xtensa_xt2000_read8,
read16: xtensa_xt2000_read16,
read32: xtensa_xt2000_read32,
copy_from: xtensa_xt2000_copy_from,
write8: xtensa_xt2000_write8,
write16: xtensa_xt2000_write16,
write32: xtensa_xt2000_write32,
copy_to: xtensa_xt2000_copy_to,
map_priv_1: 0,
map_priv_2: 0
};
/* board and partition description */
#define MAX_PHYSMAP_PARTITIONS 8
struct xtensa_xt2000_info {
char *name;
unsigned long window_addr;
unsigned long window_size;
int buswidth;
int num_partitions;
};
#define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
const struct xtensa_xt2000_info xtensa_xt2000_board_desc[PHYSMAP_NUMBER] =
{
{
"MTD flash", // name
WINDOW_ADDR, // window_addr
WINDOW_SIZE, // window_size
WINDOW_BUSWIDTH, // buswidth
1, // num_partitions
},
};
static struct mtd_partition xtensa_xt2000_partitions[PHYSMAP_NUMBER][MAX_PHYSMAP_PARTITIONS] = {
{
{
name: "User FS",
size: WINDOW_SIZE,
offset: 0,
},
},
};
struct map_info xtensa_xt2000_map[PHYSMAP_NUMBER];
int __init init_xtensa_xt2000(void)
{
int i;
struct mtd_info *mymtd;
struct mtd_partition *parts;
#ifdef CONFIG_MTD_REDBOOT_PARTS
int nr_parts = 0;
#endif
/* Initialize mapping */
for (i=0;i<PHYSMAP_NUMBER;i++) {
printk(KERN_NOTICE "xtensa_xt2000 flash device: %lx at %lx\n", xtensa_xt2000_board_desc[i].window_size, xtensa_xt2000_board_desc[i].window_addr);
memcpy((char *)&xtensa_xt2000_map[i],(char *)&basic_xtensa_xt2000_map,sizeof(struct map_info));
xtensa_xt2000_map[i].map_priv_1 = (unsigned long)ioremap_nocache(xtensa_xt2000_board_desc[i].window_addr, xtensa_xt2000_board_desc[i].window_size);
if (!xtensa_xt2000_map[i].map_priv_1) {
printk(KERN_WARNING "Failed to ioremap\n");
return -EIO;
}
xtensa_xt2000_map[i].name = xtensa_xt2000_board_desc[i].name;
xtensa_xt2000_map[i].size = xtensa_xt2000_board_desc[i].window_size;
xtensa_xt2000_map[i].buswidth = xtensa_xt2000_board_desc[i].buswidth;
//printk(KERN_NOTICE "xtensa_xt2000: ioremap is %x\n",(unsigned int)(xtensa_xt2000_map[i].map_priv_1));
}
for (i=0;i<PHYSMAP_NUMBER;i++) {
parts = &xtensa_xt2000_partitions[i][0];
mymtd = (struct mtd_info *)do_map_probe("cfi_probe", &xtensa_xt2000_map[i]);
if (mymtd) {
mymtd->module = THIS_MODULE;
xtensa_xt2000_map[i].map_priv_2 = (unsigned long)mymtd;
#ifdef CONFIG_MTD_REDBOOT_PARTS
nr_parts = parse_redboot_partitions(mymtd, &parts);
if (nr_parts > 0) {
printk(KERN_NOTICE "Found RedBoot partition table.\n");
add_mtd_partitions(mymtd, parts, nr_parts);
}
else if (nr_parts < 0)
printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
#else /* CONFIG_MTD_REDBOOT_PARTS */
add_mtd_partitions(mymtd, parts, xtensa_xt2000_board_desc[i].num_partitions);
#endif /* CONFIG_MTD_REDBOOT_PARTS */
}
else
return -ENXIO;
}
return 0;
}
static void __exit cleanup_xtensa_xt2000(void)
{
int i;
struct mtd_info *mymtd;
for (i=0;i<PHYSMAP_NUMBER;i++) {
mymtd = (struct mtd_info *)xtensa_xt2000_map[i].map_priv_2;
if (mymtd) {
del_mtd_partitions(mymtd);
map_destroy(mymtd);
}
if (xtensa_xt2000_map[i].map_priv_1) {
iounmap((void *)xtensa_xt2000_map[i].map_priv_1);
xtensa_xt2000_map[i].map_priv_1 = 0;
}
}
}
module_init(init_xtensa_xt2000);
module_exit(cleanup_xtensa_xt2000);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Alice Hennessy <ahe...@mv...>");
MODULE_DESCRIPTION("MTD map driver for Tensilica XT2000 boards");
Index: Config.in
===================================================================
RCS file: /cvsroot/xtensa/linux/drivers/mtd/maps/Config.in,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Config.in 28 Aug 2002 16:10:40 -0000 1.1.1.1
--- Config.in 28 Mar 2003 00:29:41 -0000 1.2
***************
*** 60,62 ****
--- 60,66 ----
fi
+ if [ "$CONFIG_XTENSA" = "y" ]; then
+ dep_tristate ' Tensilica XT2000 flash support' CONFIG_MTD_XT2000 $CONFIG_MTD_CFI $CONFIG_MTD_PARTITIONS
+ fi
+
endmenu
Index: Makefile
===================================================================
RCS file: /cvsroot/xtensa/linux/drivers/mtd/maps/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Makefile 28 Aug 2002 16:10:40 -0000 1.1.1.1
--- Makefile 28 Mar 2003 00:29:41 -0000 1.2
***************
*** 30,33 ****
--- 30,34 ----
obj-$(CONFIG_MTD_OCELOT) += ocelot.o
obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
+ obj-$(CONFIG_MTD_XT2000) += xtensa_xt2000.o
include $(TOPDIR)/Rules.make
|
|
From: <jgr...@us...> - 2003-03-27 19:42:49
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel In directory sc8-pr-cvs1:/tmp/cvs-serv31462/arch/xtensa/kernel Modified Files: xtensa_ksyms.c Log Message: Need to export __udivdi3 for modules using do_div(). Index: xtensa_ksyms.c =================================================================== RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/xtensa_ksyms.c,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** xtensa_ksyms.c 12 Dec 2002 22:54:43 -0000 1.3 --- xtensa_ksyms.c 27 Mar 2003 19:42:46 -0000 1.4 *************** *** 72,75 **** --- 72,76 ---- extern unsigned int __udivsi3(unsigned int, unsigned int); extern unsigned int __umodsi3(unsigned int, unsigned int); + extern unsigned long long __udivdi3(unsigned long long, unsigned long long); EXPORT_SYMBOL_NOVERS(__ashldi3); *************** *** 82,85 **** --- 83,87 ---- EXPORT_SYMBOL_NOVERS(__udivsi3); EXPORT_SYMBOL_NOVERS(__umodsi3); + EXPORT_SYMBOL_NOVERS(__udivdi3); /* |
|
From: <joe...@us...> - 2003-03-26 01:04:36
|
Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv14216/arch/xtensa/kernel
Modified Files:
gdb-stub.c
Log Message:
Remove redundant code. Update response string to "KGDB".
Index: gdb-stub.c
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/gdb-stub.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** gdb-stub.c 29 Jan 2003 06:17:59 -0000 1.6
--- gdb-stub.c 26 Mar 2003 01:04:32 -0000 1.7
***************
*** 739,759 ****
case 'q':
! if (!strncmp(input_buffer, "qxtn", 4)) {
! #if 0
! output_buffer[0] = 'L';
! output_buffer[1] = 'i';
! output_buffer[2] = 'n';
! output_buffer[3] = 'u';
! output_buffer[4] = 'x';
! output_buffer[5] = 0;
! #else
! output_buffer[0] = 'I';
! output_buffer[1] = 'S';
! output_buffer[2] = 'S';
! output_buffer[3] = '3';
! output_buffer[4] = 0;
! #endif
! strcpy(output_buffer, "XMON2.5");
! }
break;
--- 739,744 ----
case 'q':
! if (!strncmp(input_buffer, "qxtn", 4))
! strcpy(output_buffer, "KGDB");
break;
|
