Re: [Xschem] signals defined in records are also instantiated separately

[stefan s. <ste...@gm...>]

Hi Svenn,

I have ready a small change in the VHDL netlist postprocessor. This option was already in place since 2002 (!) but commented out.
In short with this option enabled if sig_type of an xschem label is:
- boolean
- real
- integer
- bit
- std_logic

then bussed nets will be declared with the base type and _vector appended.
VHDL 2008+ has integer_vector, real_vector, boolean_vector, (in addition to older bit_vector and std_logic_vector) so it is a good idea to use these _vector types.

Any other user defined type will *not* have the _vector type added in the signal declaration, unless user sets 'sig_type=mytype_vector' instead of 'sig_type=mytype'
in the schematic net label/pin.

if i have a label 'AA[3:0] in the schematic and its attributes are: name=l10 lab=AA[3:0] sig_type=rrreal
then signal declaration in netlist will be:
signal AA : rrreal (3 downto 0) ;

if attributes are: name=l10 lab=AA[3:0] sig_type=rrreal_vector
then declaration will be:
signal AA : rrreal_vector (3 downto 0) ;
  
The same is done for component/entity ports.
If you are OK with that i will commit the (small) change.

This change will not break existing VHDL designs that are using predefined (bit, std_logic, real etc) types.

Thank you for your feedback.
Stefan


On 2/19/20 2:13 PM, Svenn Are Bjerkem wrote:
> On Wed, 19 Feb 2020 at 11:04, stefan schippers <ste...@gm... <mailto:ste...@gm...>> wrote:
> 
> 
> 
>     So you suggest a flag that prevents xschem appending _vector to a bussed signal, so if sig_verbose=true a label A[7:0] with type mytype and sig_verbose=true
>     will translate to a declaration like:
> 
>     signal A : mytype(7 downto 0);
> 
>     instead of:
> 
>     signal A : mytype_vector(7 downto 0);
> 
>     Am i correct?
> 
> Yes, this assumption is correct.
> 
> 
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