Re: [Xschem] signals defined in records are also instantiated separately

[Svenn A. B. <sve...@gm...>]

On Wed, 19 Feb 2020 at 01:56, stefan schippers <ste...@gm...>
wrote:

> Hi, Svenn,
>
> This is a good catch.
> Members of records should not be declared as normally the record-signal as
> a whole is declared somewhere else.
> I can make a change in the VHDL netlister code and if a signals has a dot
> (.) in its name it should be assumed to be a record field and avoid a
> declaration for it. Do you think this should be ok?.
> To make things work you should place a net label 'my_rec' with the correct
> sig_type somewhere in the schematic (even with no connections or a
> 'noconn.sym'), so xschem will add the correct signal declaration.


but only in its name. I shot myself in the foot by assuming signal names
with a dot was a record. I had a parameter with a dot in the argument list
of the record entry and that got sed'ed away.

So far I have most records defined in external package files. I also use
the architecture declaration symbol, but a real signal label with the type
in the schematic is even better. Will the highlight function work?
Select the record definition and all the children instantiations are
glowing?


>
>
Do you think this should work?
> I am asking to you since i believe your VHDL skills are better than mine.
> Are there other special cases you know of that need to be figured out by
> the netlister?
>

we discussed the need for a separate type _vector when the [b:a] signal
notation is used. Would it be possible to have the possibility to set the
sig_type verbose and not do any magic mangling, sig_vebose=true
eventually I run into problems with matching a_type with a_type_vector.


>