Re: [Xschem] signals defined in records are also instantiated separately

[stefan s. <ste...@gm...>]

Hi, Svenn,

This is a good catch.
Members of records should not be declared as normally the record-signal as a whole is declared somewhere else.
I can make a change in the VHDL netlister code and if a signals has a dot (.) in its name it should be assumed to be a record field and avoid a declaration for it. Do you think this should be ok?.
To make things work you should place a net label 'my_rec' with the correct sig_type somewhere in the schematic (even with no connections or a 'noconn.sym'), so xschem will add the correct signal declaration.

Do you think this should work?
I am asking to you since i believe your VHDL skills are better than mine.
Are there other special cases you know of that need to be figured out by the netlister?

Thank you for reporting the issue.
Stefan

On 2/18/20 11:33 AM, Svenn Are Bjerkem wrote:
> Hi,
> If a signal is defined in a record and assigned to an instance port like this:
> 
> u_inst : someinst
> port map (
> my_sig => my_rec.mysig
> );
> 
> a signal is defined like this:
> 
> signal my_rec.mysig : std_logic;
> 
> need to run a sed script to remove those after netlisting
> sed -i  '/^signal\s\+.\+\..\+;$$/d' *.vhdl
> 
> 
> _______________________________________________
> Xschem-discuss mailing list
> Xsc...@li...
> https://lists.sourceforge.net/lists/listinfo/xschem-discuss
>