[Xschem] signals defined in records are also instantiated separately
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Brought to you by:
stef_sport_2002
|
From: Svenn A. B. <sve...@gm...> - 2020-02-18 10:33:28
|
Hi, If a signal is defined in a record and assigned to an instance port like this: u_inst : someinst port map ( my_sig => my_rec.mysig ); a signal is defined like this: signal my_rec.mysig : std_logic; need to run a sed script to remove those after netlisting sed -i '/^signal\s\+.\+\..\+;$$/d' *.vhdl |