xc3sprog-users — Generic user and developer list

Re: [Xc3sprog-users] Board XUPV5

[Adrien Prost-B. <adr...@la...>]

Thanks for your answer. I'll recheck all that tomorrow because I don't
have the board right now. And I'll rebuild from SVN.
Adrien

On Wed, 2014-05-14 at 21:07 +0200, Joris van Rantwijk wrote:
> On 2014-05-14, Adrien Prost-Boucle wrote:
> > I'm using the FPGA board XUPV5. I tried to use the tool xc3sprog to
> > program it, but it failed to regognize the IDs of 2 devices on the
> > board, one of them being the FPGA -_-
> 
> Virtex 5 should be supported by Xc3sprog. At the very least the FPGA
> type should be recognized and reported.
> 
> Which version of Xc3sprog do you use?
> What kind of JTAG cable?
> 
> Can you post the complete output of xc3sprog with verbose flag?
> 
> > - Is adding support for a board a complex task?
> 
> Depends on how similar the board is to already supported boards.
> 
> > - What information do I need to have about the board chips?
> 
> - FPGA type
> - Type of flash PROM chip (for FPGA power-on configuration)
> - Wiring between flash PROM and FPGA
> - JTAG chain layout
> - In case of an on-board JTAG programmer (USB), type of JTAG/USB chip
>   and possibly some reverse engineering of the USB communication.
> 
> Joris.

Re: [Xc3sprog-users] Board XUPV5

[Joris v. R. <jor...@jo...>]

On 2014-05-14, Adrien Prost-Boucle wrote:
> I'm using the FPGA board XUPV5. I tried to use the tool xc3sprog to
> program it, but it failed to regognize the IDs of 2 devices on the
> board, one of them being the FPGA -_-

Virtex 5 should be supported by Xc3sprog. At the very least the FPGA
type should be recognized and reported.

Which version of Xc3sprog do you use?
What kind of JTAG cable?

Can you post the complete output of xc3sprog with verbose flag?

> - Is adding support for a board a complex task?

Depends on how similar the board is to already supported boards.

> - What information do I need to have about the board chips?

- FPGA type
- Type of flash PROM chip (for FPGA power-on configuration)
- Wiring between flash PROM and FPGA
- JTAG chain layout
- In case of an on-board JTAG programmer (USB), type of JTAG/USB chip
  and possibly some reverse engineering of the USB communication.

Joris.

[Xc3sprog-users] Board XUPV5

[Adrien Prost-B. <adr...@la...>]

Hello,

I'm using the FPGA board XUPV5. I tried to use the tool xc3sprog to
program it, but it failed to regognize the IDs of 2 devices on the
board, one of them being the FPGA -_-

I usually use Xilinx's tool Impact, it works very well, but would I find
it great if the board could be programmed by xc3sprog. I'm a software
developer, C language, so it might be something I could do.

I have no knowledge of the tool internals, so I wonder:
- Is adding support for a board a complex task?
- What information do I need to have about the board chips?

Some information about the board:
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,795&Prod=XUPV5

Best regard,
Adrien

[Xc3sprog-users] Changes to XCFnnP PROM programming

[Joris v. R. <jor...@jo...>]

Hi,

I just committed two patches to the XCFnnP PROM programming code.

r759 is a small change to support splitting .BIT over multiple PROMs
(in the same way it already works for XCFnnS).

r760 is a more complicated change to support different configuration
modes with XCFnnP devices (master parallel, slave parallel, etc).
It adds a new command line option -X to xc3sprog just for this purpose.

Feel free to criticize, ridicule or plainly revert my changes if
anything is wrong.

Joris.

Re: [Xc3sprog-users] Xilinx Spartan6 (XC6SLX75) reset behaviour different from Impact

[Jiri G. <ji...@ga...>]

On 02/20/2014 11:28 PM, Joris van Rantwijk wrote:
> 
> I have succesfully used xc3sprog to program XC6SLX45 with an FTDI-based
> JTAG cable. My designs would start up correctly immediately after
> programming.
> 
> Are you programming the FPGA directly, or programming the on-board PROM?

I tried with an FTDI cable and the design did indeed start without
a manual reset. I am programming the FPGA directly.


> 
> What is the function of the reset button? Is it a design-specific reset
> on user I/O, or tied to a dedicated reset pin on the Spartan6?
> Is it a standard prototyping board with schematics available?

This is a Pender XC6S board, and I have the schematics. The reset
is just a push-button on a regular I/O, that resets the logic
and also the DCMs.

> 
> Perhaps there is an issue with the startup clock setting in bitgen.
> I believe IMPACT transparently overrides to StartUpClk:JtagClk while
> xc3sprog just stays with the setting in the bitfile. I always use
> StartUpClk:CCLK without any problems, but I can imagine this failing if
> CCLK is slower than the JTAG clock.

I have -g StartUpClk:CCLK, I will try with JtagClk. Thanks for the tip!

Jiri.

> 
> Joris.
> 
> On 2014-02-20, Jiri Gaisler wrote:
>> I noticed that when programming a certain design on a Spartan6
>> (XC6SLX75) board, the design will not start properly (no clocks)
>> until the reset button is pressed. This will reset the DCMs and the
>> clocks will start. When programming the device with Impact, the
>> design works immediately without the need for applying reset. On
>> Spartan3 and Virtex4 boards it works fine and I could not notice and
>> difference between xc3prog and Impact. Is this a known feature of
>> xc3prog or am I the only one with this problem? I am using a Digilent
>> USB-JTAG cable (Xilinx DCL10 compatible) with the -c xpc option.
>>
>> Jiri.

Re: [Xc3sprog-users] Xilinx Spartan6 (XC6SLX75) reset behaviour different from Impact

[Joris v. R. <jor...@jo...>]

On 2014-02-20, joosteto wrote:
> I actually also see this behaviour when I program the flash behind a
> spartan 3 FPGA, on a papilio board.
> As it was the first time I used xc3sprog, I just thought it normal...

It is normal when you program the flash PROM instead of the FPGA.
Programming the flash PROM via JTAG does not affect the FPGA at all, it
should just continue whatever it is doing.

xc3sprog has an option "-R" to trigger reconfiguration of the FPGA
after programming the flash PROM. However it does not work on all types
of FPGAs.

Joris.

Re: [Xc3sprog-users] Xilinx Spartan6 (XC6SLX75) reset behaviour different from Impact

[Joris v. R. <jor...@jo...>]

I have succesfully used xc3sprog to program XC6SLX45 with an FTDI-based
JTAG cable. My designs would start up correctly immediately after
programming.

Are you programming the FPGA directly, or programming the on-board PROM?

What is the function of the reset button? Is it a design-specific reset
on user I/O, or tied to a dedicated reset pin on the Spartan6?
Is it a standard prototyping board with schematics available?

Perhaps there is an issue with the startup clock setting in bitgen.
I believe IMPACT transparently overrides to StartUpClk:JtagClk while
xc3sprog just stays with the setting in the bitfile. I always use
StartUpClk:CCLK without any problems, but I can imagine this failing if
CCLK is slower than the JTAG clock.

Joris.

On 2014-02-20, Jiri Gaisler wrote:
> I noticed that when programming a certain design on a Spartan6
> (XC6SLX75) board, the design will not start properly (no clocks)
> until the reset button is pressed. This will reset the DCMs and the
> clocks will start. When programming the device with Impact, the
> design works immediately without the need for applying reset. On
> Spartan3 and Virtex4 boards it works fine and I could not notice and
> difference between xc3prog and Impact. Is this a known feature of
> xc3prog or am I the only one with this problem? I am using a Digilent
> USB-JTAG cable (Xilinx DCL10 compatible) with the -c xpc option.
> 
> Jiri.

Re: [Xc3sprog-users] Xilinx Spartan6 (XC6SLX75) reset behaviour different from Impact

[joosteto <joo...@gm...>]

I actually also see this behaviour when I program the flash behind a
spartan 3 FPGA, on a papilio board.
As it was the first time I used xc3sprog, I just thought it normal...

On 20 February 2014 22:03, Jiri Gaisler <ji...@ga...> wrote:
>
> I noticed that when programming a certain design on a Spartan6 (XC6SLX75)
> board, the design will not start properly (no clocks) until the reset button
> is pressed. This will reset the DCMs and the clocks will start. When programming
> the device with Impact, the design works immediately without the need for applying
> reset. On Spartan3 and Virtex4 boards it works fine and I could not notice and
> difference between xc3prog and Impact. Is this a known feature of xc3prog or am
> I the only one with this problem? I am using a Digilent USB-JTAG cable (Xilinx
> DCL10 compatible) with the -c xpc option.
>
> Jiri.
>
> ------------------------------------------------------------------------------
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> Read the Whitepaper.
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> _______________________________________________
> Xc3sprog-users mailing list
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[Xc3sprog-users] Xilinx Spartan6 (XC6SLX75) reset behaviour different from Impact

[Jiri G. <ji...@ga...>]

I noticed that when programming a certain design on a Spartan6 (XC6SLX75)
board, the design will not start properly (no clocks) until the reset button
is pressed. This will reset the DCMs and the clocks will start. When programming
the device with Impact, the design works immediately without the need for applying
reset. On Spartan3 and Virtex4 boards it works fine and I could not notice and
difference between xc3prog and Impact. Is this a known feature of xc3prog or am
I the only one with this problem? I am using a Digilent USB-JTAG cable (Xilinx
DCL10 compatible) with the -c xpc option.

Jiri.

[Xc3sprog-users] Patch for supporting Macronix MX25L flash

[Sébastien B. <sb...@m-...>]

Hi,

the patch below (based on papilio-loader) adds support for the Macronix MX25L flash chip used on the Papilio Pro board. Could you apply it?

Thanks,
Sébastien

Index: progalgspiflash.cpp
===================================================================
--- progalgspiflash.cpp	(revision 757)
+++ progalgspiflash.cpp	(working copy)
@@ -349,8 +349,7 @@
 
 
 
-int ProgAlgSPIFlash::spi_flashinfo_m25p(unsigned char *buf) 
- 
+int ProgAlgSPIFlash::spi_flashinfo_m25p_mx25l(unsigned char *buf, int is_mx25l)
 {
   byte fbuf[21]= {READ_IDENTIFICATION};
   int i, j = 0;
@@ -363,66 +362,90 @@
   fbuf[2] = bitRevTable[fbuf[2]];
   fbuf[3] = bitRevTable[fbuf[3]];
 
-  switch (fbuf[1])
-    {
-    case 0x20:
-      fprintf(stderr, "Found Numonyx M25P Device, Device ID 0x%02x%02x\n",
-              fbuf[1], fbuf[2]);
-      switch (fbuf[2])
-        {
-        case 0x11:
-          pages = 512;
-          sector_size = 32768; /* Bytes = 262144 bits*/
-          break;
-        case 0x12:
-          pages = 1024;
-          break;
-        case 0x13:
-          pages = 2048;
-          break;
-        case 0x14:
-          pages = 4096;
-          break;
-        case 0x15:
-          pages = 8192;
-          break;
-        case 0x16:
-          pages = 16384;
-          break;
-        case 0x17:
-          pages = 32768;
-          sector_size = 131072; /* Bytes = 1 Mi Bit*/
-          break;
-        case 0x18:
-          pages = 65536;
-          sector_size = 262144; /* Bytes = 2 Mi Bit*/
-          break;
-        default:
-          fprintf(stderr,"Unexpected M25P size ID 0x%02x\n", buf[2]);
-          return -1;
-        }
-      break;
+  if(is_mx25l) {
+    switch (fbuf[1])
+      {
+      case 0x20:
+        fprintf(stderr, "Found Macronix MX25L Device, Device ID 0x%02x%02x\n",
+                fbuf[1], fbuf[2]);
+        switch (fbuf[2])
+          {
+          case 0x17:
+            pages = 262144;
+            sector_size = 65536; 
+            break;
+          default:
+            fprintf(stderr,"Unexpected MX25L size ID 0x%02x\n", buf[2]);
+            return -1;
+          }
+        break;
 
-    case 0xba:
-      fprintf(stderr, "Found Numonyx N25Q Device, Device ID 0x%02x%02x\n",
-              fbuf[1], fbuf[2]);
-      switch (fbuf[2])
-        {
-        case 0x18:
-          pages = 65536;
-          sector_size = 65536;
-          break;
-        default:
-          fprintf(stderr,"Unexpected N25Q size ID 0x%02x\n", buf[2]);
-          return -1;
-        }
-      break;
+      default:
+        fprintf(stderr,"MX25L: Unexpected RDID upper Device ID 0x%02x\n", fbuf[1]);
+        return -1;
+      }
+  } else {
+    switch (fbuf[1])
+      {
+      case 0x20:
+        fprintf(stderr, "Found Numonyx M25P Device, Device ID 0x%02x%02x\n",
+                fbuf[1], fbuf[2]);
+        switch (fbuf[2])
+          {
+          case 0x11:
+            pages = 512;
+            sector_size = 32768; /* Bytes = 262144 bits*/
+            break;
+          case 0x12:
+            pages = 1024;
+            break;
+          case 0x13:
+            pages = 2048;
+            break;
+          case 0x14:
+            pages = 4096;
+            break;
+          case 0x15:
+            pages = 8192;
+            break;
+          case 0x16:
+            pages = 16384;
+            break;
+          case 0x17:
+            pages = 32768;
+            sector_size = 131072; /* Bytes = 1 Mi Bit*/
+            break;
+          case 0x18:
+            pages = 65536;
+            sector_size = 262144; /* Bytes = 2 Mi Bit*/
+            break;
+          default:
+            fprintf(stderr,"Unexpected M25P size ID 0x%02x\n", buf[2]);
+            return -1;
+          }
+        break;
 
-    default:
-      fprintf(stderr,"M25P: Unexpected RDID upper Device ID 0x%02x\n", fbuf[1]);
-      return -1;
-    }
+      case 0xba:
+        fprintf(stderr, "Found Numonyx N25Q Device, Device ID 0x%02x%02x\n",
+                fbuf[1], fbuf[2]);
+        switch (fbuf[2])
+          {
+          case 0x18:
+            pages = 65536;
+            sector_size = 65536;
+            break;
+          default:
+            fprintf(stderr,"Unexpected N25Q size ID 0x%02x\n", buf[2]);
+            return -1;
+          }
+        break;
 
+      default:
+        fprintf(stderr,"M25P: Unexpected RDID upper Device ID 0x%02x\n", fbuf[1]);
+        return -1;
+      }
+  }
+
   pgsize = 256;
 
   if (fbuf[3] == 0x10)
@@ -489,8 +512,11 @@
       res = spi_flashinfo_amic_quad(fbuf);
       break;
     case 0x20:
-      res = spi_flashinfo_m25p(fbuf);
+      res = spi_flashinfo_m25p_mx25l(fbuf, 0);
       break;
+    case 0xc2:
+      res = spi_flashinfo_m25p_mx25l(fbuf, 1);
+      break;
     case 0x89:
       res = spi_flashinfo_s33(fbuf); 
       break;
@@ -1145,6 +1171,7 @@
   case 0x1f: /* Atmel */
     return program_at45(pfile);
   case 0x20: /* Numonyx */
+  case 0xc2: /* Macronix */
   case 0x30: /* AMIC */
   case 0x40: /* AMIC Quad */
   case 0xef: /* Winbond */
@@ -1335,6 +1362,7 @@
   case 0x1f: /* Atmel */
     return erase_at45();
   case 0x20: /* Numonyx */
+  case 0xc2: /* Macronix */
   case 0x30: /* AMIC */
   case 0x40: /* AMIC Quad */
   case 0x89: /* Intel */
Index: progalgspiflash.h
===================================================================
--- progalgspiflash.h	(revision 757)
+++ progalgspiflash.h	(working copy)
@@ -65,7 +65,7 @@
   int spi_flashinfo_amic_quad (unsigned char * fbuf);
   int spi_flashinfo_w25 (unsigned char * fbuf);
   int spi_flashinfo_at45(unsigned char * fbuf);
-  int spi_flashinfo_m25p(unsigned char * fbuf);
+  int spi_flashinfo_m25p_mx25l(unsigned char * fbuf, int is_mx25l);
   int spi_flashinfo_sst(unsigned char * fbuf);
   int wait(byte command, int report, int limit, double *delta);
   int wait(byte command, byte mask, byte value, int report, int limit, double *delta);

[Xc3sprog-users] Spansion Flash

[joosteto <joo...@gm...>]

Hello,

I build my first FPGA-board (mostly a copy from papilio), but the
FLASH memory I bought wasn't supported by xc3sprog.

Manufacturer ID: 0x01, Spansion

So I wrote the patch below.
I couldn't find any details as to how to interpret the 'capacity ID'
(fbuf[3]) in the datasheet, so I only added the value I know about
(8Mb, capacity ID=0x01).

Index: progalgspiflash.h
===================================================================
--- progalgspiflash.h   (revision 757)
+++ progalgspiflash.h   (working copy)
@@ -60,6 +60,7 @@
   int xc_user(byte *in, byte *out, int len);
   int spi_xfer_user1(uint8_t *last_miso, int miso_len, int miso_skip,
                     uint8_t *mosi, int mosi_len, int preamble);
+  int spi_flashinfo_spansion (unsigned char * fbuf);
   int spi_flashinfo_s33 (unsigned char * fbuf);
   int spi_flashinfo_amic (unsigned char * fbuf);
   int spi_flashinfo_amic_quad (unsigned char * fbuf);
Index: progalgspiflash.cpp
===================================================================
--- progalgspiflash.cpp (revision 757)
+++ progalgspiflash.cpp (working copy)
@@ -81,7 +81,20 @@
   if(fp_dbg)
     fclose(fp_dbg);
 }
-
+int ProgAlgSPIFlash::spi_flashinfo_spansion(unsigned char *buf){
+  fprintf(stderr, "Found Spansion Device, Device ID %02x, memory type
%02x, capacity %02x\n",
+         buf[1], buf[2], buf[3]);
+  switch (buf[3]){
+  case 0x01:
+    pages = 4096;
+    break;
+  default:
+    fprintf(stderr, "Unknown Spansion capacity ID %02x\n", buf[3]);
+    return -1;
+  }
+  pgsize = 256;
+  return 1;
+}
 int ProgAlgSPIFlash::spi_flashinfo_s33(unsigned char *buf)
 {
   fprintf(stderr, "Found Intel Device, Device ID 0x%02x%02x\n",
@@ -468,6 +481,9 @@

   switch (fbuf[0])
     {
+    case 0x01:
+      res = spi_flashinfo_spansion(fbuf);
+      break;
     case 0x1f: {
         switch (fbuf[1]>> 5) /* Family code*/ {
         case 1:
@@ -1144,6 +1160,7 @@
   switch (manf_id) {
   case 0x1f: /* Atmel */
     return program_at45(pfile);
+  case 0x01: /* Spansion */
   case 0x20: /* Numonyx */
   case 0x30: /* AMIC */
   case 0x40: /* AMIC Quad */

Re: [Xc3sprog-users] xc3s500e, waveshare board and xilinx parallel III cable problem

[Sergej P. <ml...@se...>]

At Mon, 20 Jan 2014 15:03:25 +0100,
bo...@el... wrote:
>
>     Sergej> '001010000010100100000001' INFO:iMPACT:1207 - Expected Capture =
>     Sergej> '101010101010XXXXXXXXX001'
>
>     Sergej> and detects unknown chip and xcf04s chip.
>
> So I doubt the adapter, or you have a fake XC3S.
>
> Any chance to test with another adapter?

I'll try to find another jtag.

If I do boundary scan while nconfig button is pressed, impact detects
chip as generated_unknown_0_6, if not pressed then as
generated_unknown_0_4.

If I press nconfig, release it and quickly do boundary scan, it
detected as generated_unknown_0_5.

Do you know what these numbers mean?

Re: [Xc3sprog-users] xc3s500e, waveshare board and xilinx parallel III cable problem

[<bo...@el...>]

>>>>> "Sergej" == Sergej Pupykin <ml...@se...> writes:

...
    Sergej> Impact says something similar I think:

    Sergej> INFO:iMPACT:1206 - Instruction Capture =
    Sergej> '001010000010100100000001' INFO:iMPACT:1207 - Expected Capture =
    Sergej> '101010101010XXXXXXXXX001'

    Sergej> and detects unknown chip and xcf04s chip.

So I doubt the adapter, or you have a fake XC3S.

Any chance to test with another adapter?
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Re: [Xc3sprog-users] xc3s500e, waveshare board and xilinx parallel III cable problem

[Sergej P. <ml...@se...>]

At Fri, 17 Jan 2014 20:25:12 +0100,
bo...@el... wrote:
>     Sergej> with Xilinx Parallel Cable III
> Is it the XILINX cable or a clone? Is it a lob cable or not?
> Maybe the logic levels are not right?

It is chinese clone I think. Vendor says "Hardware is based on 2 pcs
of 74HC125D".

>     Sergej> $ detectchain -c pp Found Xilinx Parallel Cable III JTAG loc.: 0
>     Sergej> IDCODE: 0x000c0003 not found in 'built-in device list'.  JTAG
>     Sergej> loc.: 1 IDCODE: 0xd5046093 Desc: XCF04S Rev: M IR length: 8
> 
> You can download the Xilinx impact package, install and set up and test if
> it works that way. Or test with another JTAG package that talks to your
> cable. Let me know if the chain is detected by some other tool with your
> setup.

Impact says something similar I think:

INFO:iMPACT:1206 - Instruction Capture = '001010000010100100000001'
INFO:iMPACT:1207 - Expected    Capture = '101010101010XXXXXXXXX001'

and detects unknown chip and xcf04s chip.

> Test also with "-T0". It will show if the bad ID repeats with repeated
> detections.

With -T0 key it says:

Found Xilinx Parallel Cable III
Cannot find device having IDCODE=00c0003 Revision A
Running IR_TEST 2147483647  times
IR len = 8
0x01 binary 00000001
........................................................................................
........................................................................................
........................................................................................
........................................................................................
........................................................................................
........................................................................................
........................................................................................
........................................................................................
....................................

etc, I did not wait for 2147483647 times and press Ctrl+C after few
screens of dots.


> 
>     Sergej> I added "000c0003 6 0x0009 XC3S500E" to devlist.txt but it
>     Sergej> obviously does not help.
> 
> Run with -v to see if your changed devlist.txt is picked up.

Yes, devlist.txt looks picked up.
1st error - built-in devlist.txt
2nd error - my modified devlist.txt

>     Sergej> Programming gives
> 
>     Sergej> Cannot find device having IDCODE=00c0003 Revision A
> 
>     Sergej> or
> 
>     Sergej> JTAG chainpos: 0 Device IDCODE = 0x000c0003 Desc: XC3S500E
>     Sergej> Sorry, can't program device 'XC3S500E' from manufacturer 0x01 A
>     Sergej> more recent release may be able to.
> 
>     Sergej> errors.

I've found that there are SS, SPI, and JTAG modes. Can xc3s500e be
configured as SS or SPI, but LPT cable does not support such modes?

As I understand xc3s500e boots from flash and executes preinstalled
joystick example flashing leds depending on joystick position.

Re: [Xc3sprog-users] xc3s500e, waveshare board and xilinx parallel III cable problem

[<bo...@el...>]

>>>>> "Sergej" == Sergej Pupykin <ml...@se...> writes:

    Sergej> Hello,

    Sergej> I am trying to use WaveShare Open3S500E board
 
    Sergej> http://www.wvshare.com/product/Open3S500E-Standard.htm

    Sergej> with Xilinx Parallel Cable III
Is it the XILINX cable or a clone? Is it a lob cable or not?
Maybe the logic levels are not right?

    Sergej> $ detectchain -c pp Found Xilinx Parallel Cable III JTAG loc.: 0
    Sergej> IDCODE: 0x000c0003 not found in 'built-in device list'.  JTAG
    Sergej> loc.: 1 IDCODE: 0xd5046093 Desc: XCF04S Rev: M IR length: 8

    Sergej> Searching gives me some result about broken TDI/TDO connectors,
    Sergej> EMI, etc. Is there any way to diagnose this problem without
    Sergej> digging hardware using osciloscope?

You can download the Xilinx impact package, install and set up and test if
it works that way. Or test with another JTAG package that talks to your
cable. Let me know if the chain is detected by some other tool with your
setup.

Test also with "-T0". It will show if the bad ID repeats with repeated
detections.

    Sergej> I added "000c0003 6 0x0009 XC3S500E" to devlist.txt but it
    Sergej> obviously does not help.

Run with -v to see if your changed devlist.txt is picked up.

    Sergej> Programming gives

    Sergej> Cannot find device having IDCODE=00c0003 Revision A

    Sergej> or

    Sergej> JTAG chainpos: 0 Device IDCODE = 0x000c0003 Desc: XC3S500E
    Sergej> Sorry, can't program device 'XC3S500E' from manufacturer 0x01 A
    Sergej> more recent release may be able to.

    Sergej> errors.
Just some ideas.
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

[Xc3sprog-users] xc3s500e, waveshare board and xilinx parallel III cable problem

[Sergej P. <ml...@se...>]

Hello,

I am trying to use WaveShare Open3S500E board

http://www.wvshare.com/product/Open3S500E-Standard.htm

with Xilinx Parallel Cable III

$ detectchain -c pp 
Found Xilinx Parallel Cable III
JTAG loc.:   0  IDCODE: 0x000c0003  not found in 'built-in device list'.
JTAG loc.:   1  IDCODE: 0xd5046093  Desc:                         XCF04S Rev: M  IR length:  8

Searching gives me some result about broken TDI/TDO connectors, EMI,
etc. Is there any way to diagnose this problem without digging
hardware using osciloscope?

I added "000c0003      6 0x0009 XC3S500E" to devlist.txt but it
obviously does not help.

Programming gives

Cannot find device having IDCODE=00c0003 Revision A

or

JTAG chainpos: 0 Device IDCODE = 0x000c0003	Desc: XC3S500E
Sorry, can't program device 'XC3S500E' from manufacturer 0x01 A more recent release may be able to.

errors.

Re: [Xc3sprog-users] Verbose as default

[Uffe J. <uf...@uf...>]

On 2013-12-12 17:53, bo...@el... wrote:
>
> I tend to make xc3sprog verbose by default and to replace the -v option by a
> -q option to make xc3sprog non-verbose.
>

+1

> Any objections?
>

Please go ahead - I'm hit by this quite ofent too - thanks

/Uffe

[Xc3sprog-users] Verbose as default

[<bo...@el...>]

Hello,

I often forget to give the -v argument and when flashing big SPI parts, the
silence on the terminal while programming give a long time of doubts whether
things run as expected.

I tend to make xc3sprog verbose by default and to replace the -v option by a
-q option to make xc3sprog non-verbose.

Any objections?

Thanks
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

[Xc3sprog-users] Programming the CoolRunner-II CPLD Starter Kit

[Sidney C. <si...@ji...>]

Hi all,

Is it currently possible to use xc3sprog with the CoolRunner-II CPLD
Starter Kit, via the USB port that is also used to power the device?

"lsusb" lists the device as follows:

Bus 001 Device 008: ID 1443:0007 Digilent CoolRunner-II CPLD Starter Kit

NB. the board also has a standard 6-pin JTAG header which works fine,
but I'd prefer to have only a single cable to the board if possible.

Kind regards, Sidney

Re: [Xc3sprog-users] Programming Spartan-II

[Arnim L. <arn...@gm...>]

Following up on this topic with latest results from iMPACT...

Surprisingly, the xc2s100 is identified by iMPACT as an xcv100 during
JTAG chain detection. A warning goes by when I assign the bit file to
the FPGA since it was compiled for xc2s100. Nevertheless the FPGA gets
programmed successfully. Weird.
Dumped an SVF file for this setup and ran it through urjtag - success.

Checking the BSDL descriptions for xc2s100 and xcv100 revealed that both
IDCODEs are identical except for the stepping/version part.
Said observation and this PCN
  http://www.xilinx.com/bvdocs/notifications/pcn2001-08.pdf
suggests, that I'm actually looking at a Virtex xcv100 device that's
packaged as Spartan-II xc2s100 (AFS on topmark).

Other sources mention that Spartan-II and Virtex are compatible for the
bit files. Probably not regarding for the configuration details... Since
xc3sprog doesn't support Virtex I can't figure this out with xc3sprog.
But the working SVF file for xcv100 (in contrast to a failing SVF file
that's been generated for xc2s100) seconds this assumption.


Cheers,
Arnim

Re: [Xc3sprog-users] Programming Spartan-II

[Arnim L. <arn...@gm...>]

Am 15.09.2013 22:46, schrieb bo...@el...:
>>>>>> "Arnim" == Arnim Läuger <arn...@gm...> writes:
> 
> 
>     Arnim> But in both cases I can't download the bit-file directly to the
>     Arnim> xc2s100.  It won't come up with the new configuration.
> 
> 
> Read back a working a non-working PROM image as a bin file and compare.

The point is there are only "working PROM images".
Mapping my observations to the ISE flow:

  Compile
     |
     v
   bitgen  ->  test.bit & test.bin (startupClock=JtagClk)
                  |
                  v
                iMPACT -> test.mcs (startupClock=Cclk)


Downloading test.bit (with startupClock=JtagClk) to the FPGA doesn't
yield any effect:
- FPGA remains unconfigured if PROM is erased
- FPGA keeps current configuration if an image was previously loaded
  from PROM

Downloading test.mcs to PROM is always pass, the FPGA is configured
after power cycle. Reading the PROM in this state results in a bin file
that's identical to test.bin (if generated with startupClock=Cclk).


This is where I'm currently stuck. Some potential causes might be:
- the bit file is wrong
- the way it's downloaded is wrong
- the FPGA doesn't accept configuration at all via JTAG
Guess it's the last one, but my experience with Spartan-II is quite
limited. Downloading directly to FPGA always worked for Spartan 3 or
similar modern devices.

In parallel I'm looking for a dongle that's compatible with iMPACT and
will see how things are there.

Cheers,
Arnim

Re: [Xc3sprog-users] How to program a PROM memory (XCFxxS).?

[Luis A. G. <gua...@gm...>]

2013/9/15 Joris van Rantwijk <jor...@jo...>:
> On 2013-09-15, Luis Alberto Guanuco wrote:
>> $ ./xc3sprog -v -c ftdiphr s3board_prom.mcs:W:0:MCS: -p 1 -R
>
> I prefer to program BIT files, not MCS or HEX or anything else.
> There is some controversy about the order of bits in MCS files, but for
> BIT files it is always the same.
>
> The best idea is probably to program the exact same file that was
> working when you programmed it directly to the FPGA.

I tried to program the PROM with the same BIT file used to program the
FPGA but I don't achieve do it.

>> but when I change the FPGA boot mode (M[2:0] from JTAG to Master
>> Serial) seems that the PROM doesn't load to the FPGA.
>
> Master serial is good. Then power-cycle the board of course.
> How do you known the FPGA does not load the PROM? Do you not get the
> DONE indication from the FPGA?
>

After run the line command I turn off the board, I change the boot
mode (jtag->serial mode). Then I powered the board  but the DONE led
doesn't light up.

luis@luis-laptop:build$ ./xc3sprog -v -c ftdiphr s3demo.bit -p 1
XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 747 $ OS: Linux
...
Using devlist.txt
Using cablelist.txt
Cable ftdiphr type ftdi VID 0x0403 PID 0x6010 dbus data 00 enable 0b
cbus data 00 data 00
Using Libftdi, Using JTAG frequency   6.000 MHz from undivided clock
JTAG chainpos: 1 Device IDCODE = 0x05045093 Desc: XCF02S
Erasing......done
Erase time 3159.1 ms
Programming does not end at block boundary (nbits = 1047616), padding
Programming block    255/   256 at XCF frame 0x1fe0.done
Programming time 2804.8 ms
Verify block    255/   256 at XCF frame 0x1fe0
Success! Verify time 806.0 ms
USB transactions: Write 792 read 779 retries 1789

> Which board are you using? Are you sure the PROM is correctly
> connected on the board? For example, have you tested programming the
> PROM with IMPACT?

I using the S3BORD[0] (by digilent inc.).

I probed the change commented by Arnim and it works!

The command line used is,
luis@luis-laptop:build$ ./xc3sprog -v -c ftdiphr design.mcs:w:0:IHEX: -p 1 -R
XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 747 $ OS: Linux
...
Using devlist.txt
Using cablelist.txt
Cable ftdiphr type ftdi VID 0x0403 PID 0x6010 dbus data 00 enable 0b
cbus data 00 data 00
Using Libftdi, Using JTAG frequency   6.000 MHz from undivided clock
JTAG chainpos: 1 Device IDCODE = 0x05045093 Desc: XCF02S
Erasing......done
Erase time 3159.3 ms
Programming does not end at block boundary (nbits = 1047616), padding
Programming block    255/   256 at XCF frame 0x1fe0.done
Programming time 2812.9 ms
Verify block    255/   256 at XCF frame 0x1fe0
Success! Verify time 787.9 ms
USB transactions: Write 793 read 779 retries 1785

Thanks very much Arnim!

>
> Joris.



-- 
P Antes de imprimir, piense en su responsabilidad y compromiso con el
MEDIO AMBIENTE

Re: [Xc3sprog-users] Programming Spartan-II

[<bo...@el...>]

>>>>> "Arnim" == Arnim Läuger <arn...@gm...> writes:


    Arnim> But in both cases I can't download the bit-file directly to the
    Arnim> xc2s100.  It won't come up with the new configuration.


Read back a working a non-working PROM image as a bin file and compare.
I guess we have a bit order problem...

Bye
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Re: [Xc3sprog-users] How to program a PROM memory (XCFxxS).?

[Joris v. R. <jor...@jo...>]

On 2013-09-15, Luis Alberto Guanuco wrote:
> $ ./xc3sprog -v -c ftdiphr s3board_prom.mcs:W:0:MCS: -p 1 -R

I prefer to program BIT files, not MCS or HEX or anything else.
There is some controversy about the order of bits in MCS files, but for
BIT files it is always the same.

The best idea is probably to program the exact same file that was
working when you programmed it directly to the FPGA.

> but when I change the FPGA boot mode (M[2:0] from JTAG to Master
> Serial) seems that the PROM doesn't load to the FPGA.

Master serial is good. Then power-cycle the board of course.
How do you known the FPGA does not load the PROM? Do you not get the
DONE indication from the FPGA?

Which board are you using? Are you sure the PROM is correctly
connected on the board? For example, have you tested programming the
PROM with IMPACT?

Joris.

Re: [Xc3sprog-users] How to program a PROM memory (XCFxxS).?

[Arnim L. <arn...@gm...>]

> I can not to program the PROM correctly but I can to program the FPGA
> directly. I was read the "manual page site" and I try to program the
> memory...
> 
> luis@luis-laptop:build$ ./xc3sprog -v -c ftdiphr s3board_prom.mcs:W:0:MCS: -p 1 -R

Have you tried IHEX instead of MCS? The manual mentions that PROMGEM MCS
files fall into this category. At least it's the setting which works for
me when downloading to the PROM.

Arnim