I've decided that this thing is ready to drop the beta tag and is now declared Stable. There's one more bug I've got to fix before I make a release, but there will be a release in the coming days. Note it will only be a source code release, but still.

I'll have a more informative news report of what's gone on the past year or so whenever I make the release.

I have made a number of changes so that this project will compile very easily with OpenBSD and such Unix systems.
of the changes made are
1. yasm has replaced fasm for test assembly code.
2. the "obj" directory has been renamed "objs" so that make doesn't try anything dumb.
3. line endings have been changed from DOS style to Unix style.

I am now using the Doxygen documentation system. Docs should be up very soon, and a preview can already be had in SVN

A new branch has been made in SVN. I have made it capable of having multiple CPUs and have added memory locking to PhysMemory, and many other changes discussed in a text file in the branch(called this_branch.txt)

This branch will eventually be switched to as the main version, as quite a few bugs were also fixed...

x86Lib has finally made a release... It is v0.5.0 Alpha and has all 8086 instructions.

The implementation guide is also finished and can be viewed at http://x86lib.sf.net/?page=doc

Finally, there is now almost full 8086 emulation(there are still a few bugs, but nothing major) all opcodes are added...but a lot of them need to be tested better...

A release should be in the near future...I expect something by the end of this month(January)... I really want to make a simple implementation guide first though...

Ok, their is now a WIP website at http://x86lib.sf.net

Ok, there is no development guide made yet(that is something I'd have to do...) but if you want to try to hack about and help with this project, here is what can be done...
--bitwise instructions and their generic versions (like how and_rm8_r8 calls And8()) (including shift instructions)
--A small document or whatever giving a list of implemented and unimplemented opcodes
--Help testing opcodes (I have yet to really thoroughly test anything...)
--Portability concerns... if I have anything non-portable, I'd like to know about it...
--FPU...if you'd be interested about adding support, email me, and we can talk about it..
--LEA/LDS/LES implement those opcodes...
--CMPS and friends, note that this may be more work than you think, as I have yet to make such an instruction, and REPE/REPNE have not been tested...(only REP)
--XCHG and XLAT instructions...... read more

Though (probably) over a hundred opcodes still need to be implemented, the main stepping stones for everything is implemented and proper adjustments made in order for them to be implemented. Conditional processing(sub and jcc) is done. ModRM instructions are very easy to implement now(and a few are already). String instructions and REP work perfectly. There are loops and calls and such flow control. External interrupts work. Port instructions work. And last, but not least, segment overrides work.... read more