#83 Sensitivity list error

[stu-e]

VHDL code:
p_ABS : process(CLOCK, RESET)
begin
if RESET = '1' then
ASIGNAL <= (ASIGNAL'high => '1', others => '0');

elsif rising\_edge\(CLOCK\) then

end if;

end process P_ABS;

Causes parser warning in problems pane:
Signal ASIGNAL not in sensitivity list

ASIGNAL'high is a tick attribute and not a signal and therefore has no place in the sensitivity list.