#82 Case sensitivity for parser

[stu-e]

This example VHDL code causes an error to be flagged in the problems pane:
p_ABS : process(CLOCK,RESET)
begin
if RESET = '1' then

    elsif rising\_edge\(CLOCK\) then

    end if;
end process P\_ABS;

Error:
line (37): identifiers don't match: p_ABS/=P_ABS

VHDL is not case sensitive and this should be demoted to a warning.