A new release of the Xeon Phi code generator which suceeds in vectorising some constructst that were previously unvectorisable has been unploaded in the latest install.jar.
The Xeon Phi code generator now supports some of the more novel features of the architecture like prefetching, gather instruction and fused multiply accumulate operations.
The Xeon Phi code generator is now incorporated in the standard install.zip file. It uses the updated ILCG system to optimise the abstract syntax tree to make use of the gather instructions on the MIC. To compile to the Xeon Phi use the option -cpuMIC . It works as a cross compiler and requires that you have on your path a version of gcc and as that have been renamed to micgcc and micas
The zip file installexperimental507.zip has a version with SIMD code generation for the MIC which is much faster than the previous MIC version. It has also fixed a bug in the use of mis matched string parameter sizes for the nasm assembler code generators.
A basic version of support for the Intel MIC is included in the experimental release. This may have had knock on effects on the AVX version so if you want to use the AVX version stick to the stable release.
Some bugs were discovered in the input and output of enumerated types and fixed today.
We have added an improved listing file facility so that the listings now say which lines in your programme have been parallelised
New release today which has better performance in the optimiser for the AVX32 when opt levels >0 are used