From: Vince W. <vi...@cs...> - 2010-01-03 22:57:01
|
On Sun, 3 Jan 2010, Julian Seward wrote: > > v7 is really the minimum supported target. The JIT produces mostly > v5 instructions but some v6 (load 16-bit immediates into a lower/upper > register half), and a few v7 (ldrex{,b,w,d} and strex{,b,w,d}) to do > with atomic memory accesses, and it also assumes the presence of VFP. > So it's not surprising it SIGILLd on a v5 cpu. My test cases don't use atomic memory accesses, so changing the #if 0 in VEX/priv/host_arm_defs.c to #if 1 ( to not generate the thumb2 16-bit immediate instructions ) was enough to get things running on my test system. I also had to fix my test cases to not use the blx opcode, and to use the new EABI syscall style. The tests seems to run correctly now. Would it be OK to commit the exp-bbv arm test cases? The only change made outside of the exp-bbv tree is to add the exp-bbv/tests/arm-linux/Makefile line to the master configure.in file. I can post the updated patch if others want to review first. Vince |