From: Martin L. <mar...@gm...> - 2003-08-24 20:40:47
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On Sun, Aug 24, 2003 at 08:39:56PM +0200, Pedro Lopez-Cabanillas wrote: > El Domingo, 24 de Agosto de 2003 15:18, Martin Langer escribió: > > On Sun, Aug 24, 2003 at 01:24:47PM +0200, Karsten Wiese wrote: > > > it's an XCS20XL. > > > > According to http://www.xilinx.com/bvdocs/publications/ds060.pdf the PROM > > size of the XCS20XL is 179160 Bits (page 33). That's exactly the size of > > our file (without pre padding bits). > > > > But our header information looks different to the described Spartan (XL) > > header in the documents (xapp098.pdf, page 9). That's bad. > > Because for Spartan-II, i'm using LSB-first translation into ascii bits. So, > the hex value 0xaa995566 is translated to ascii bits: > 0101 0101 1001 1001 1010 1010 0110 0110 > I've done that because the examples for spartan/virtex rbt files all have this > format. > > But if you look to the hex representation in us428fw8001.h > char Daud0006[ 4096] = > { 0xFF, 0x20, 0x2B, 0xBD, 0x1F, 0x5B, 0xFF, 0xFE, 0xFF, 0xF7, 0xB5, 0xFB, > 0xFE, 0x5F, 0xD7, 0xFB, > It fits on the layout for Spartan/XL data stream format in serial mode, > ds060.pdf, page 32, table 16. > > Data type Serial Mode > Fill byte 11111111b > Preamble 0010b > Length count 0x02bbd1 > Fill bits 1111b > > The length count (179153 dec) does not match. But if you look to the example > in xapp098.pdf, page 8, it says Bits: 247968, and the length count field is > 0x3C899 (247961 dec), again 7 bits shorter. > > We need to investigate deeper on this. > ds060.pdf, page 32, at the end of the first paragraph: [...] The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. [...] Let's assume that the last seven data bits there have no CRC checking And if the CRC checking depends on the length value in the header it's necessary to make it 7 bits shorter. That could be a solution on Spartan/Spartan-XL, or? bye, martin |