Re: [UrJTAG-dev] Related files

[Waschk,Kolja <ur...@ix...>]

> custom logic inside an FPGA. The goal is to have a generic driver that
> circumvents reading and writing of external memory via the BSR. A small

Hi Arnim, are you working with Altera FPGAs, eventually using the
sld_virtual_jtag megafunction? Somewhere down on my to-do list was
reverse-engineering of the communication with that logic... but I was
waiting for JTAG tools to become a better base for such tasks then ;)

http://forum.niosforum.com/forum/index.php?showtopic=4697&pid=18031&mode=threaded

> If part of the UrJTAG tarball, the VHDL should be kept away from the
> src/ tree. Would a new directory like 'contrib' be the right place? What
> do you think?

More things to be put in that place come to mind - like cable
schematics, firmware and VHDL, and code for target CPUs for boosting
data download to target memory... could be put in a contrib or extra or
glue or target or interface or linkup or ...

Kolja