#18 Error in parsing unpacked XDL

[Jacob Couch]

Difficulty parsing nets. It seems that I'm having a problem parsing power nets after they have been run through the unpacker.

Enclosed is a copy of the net that is causing the error, the outpin (line 7031) is the issue according the error log, and the corresponding instance.

Error:
xdl.unpacked:7031.51-52: syntax error, unexpected $undefined, expecting IDENTIFIER

Net:
net "GLOBAL_LOGIC1_0" power,
outpin "XDL_DUMMY_INT_X8Y42_TIEOFF_X8Y42:KEEP1VCC:" 1,
inpin "i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp:A6LUT:i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/I_SRL_T2.U_SRL" A1,
inpin "i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp:A6LUT:i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/I_SRL_T2.U_SRL" A6
;

Instance:
inst "XDL_DUMMY_INT_X8Y42_TIEOFF_X8Y42:KEEP1VCC:" "KEEP1VCC", unplaced, cfg "KEEP1VCC::#OFF";

[Aaron]

It looks like the pin name is incorrect, "1" is not a valid identifier for the XDL parser. Is this XDL accepted by the Xilinx tools?

[Jacob Couch]

Not fully, but if the design is unpacked using torc, that is the name of the pin in the xdlrc.

On Jul 22, 2015 11:39 PM, Aaron <arwood82@users.sf.net> wrote:

It looks like the pin name is incorrect, "1" is not a valid identifier for the XDL parser. Is this XDL accepted by the Xilinx tools?

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[bugs:#18] Error in parsing unpacked XDL

Status: open
Group: None
Created: Wed Jul 22, 2015 07:47 PM UTC by Jacob Couch
Last Updated: Wed Jul 22, 2015 07:47 PM UTC
Owner: nobody
Attachments:

• chipscope.xdl.unpacked (sourceforge.net) (3.2 MB; application/octet-stream)

Difficulty parsing nets. It seems that I'm having a problem parsing power nets after they have been run through the unpacker.

Enclosed is a copy of the net that is causing the error, the outpin (line 7031) is the issue according the error log, and the corresponding instance.

Error:
xdl.unpacked:7031.51-52: syntax error, unexpected $undefined, expecting IDENTIFIER

Net:
net "GLOBAL_LOGIC1_0" power,
outpin "XDL_DUMMY_INT_X8Y42_TIEOFF_X8Y42:KEEP1VCC:" 1,
inpin "i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp:A6LUT:i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/I_SRL_T2.U_SRL" A1,
inpin "i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp:A6LUT:i_vio/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/I_SRL_T2.U_SRL" A6
;

Instance:
inst "XDL_DUMMY_INT_X8Y42_TIEOFF_X8Y42:KEEP1VCC:" "KEEP1VCC", unplaced, cfg "KEEP1VCC::#OFF";

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