#3 Module inputs non functional.

[Tobin Richard]

Using the preview snapshot of 2.0 inputs and outputs of modules
don't seem to be functional.

For example: the circuit that first loads when tkGate starts contains
the module REGS which takes the clock signal as one of its inputs.
A probe on the wire from the clock shows the clock signal but a
probe on the wire inside the module does not.

[Tobin Richard]

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Upon closer inspection it would appear that modules inputs do work but
that traces can't be generated for them.

[Jeffery Hansen]

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Yes, the inputs do work in the simulation and I know there
is a problem with the probes. All nets that are directly
connected via an "ordinary port" are merged into a single
net. In order to fix the probe problem, I need to add code
to record the aliases for that merged net when looking up a
wire for a probe.