SystemVerilog Verification Library

Status: Planning

Brought to you by: bryan_morris, neil_johnson

Last Update: 2013-03-22

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SystemVerilog Verification Library
A set of utility classes written in SystemVerilog specifically geared towards ASIC Verification. Also includes a set of tools written for developing in SystemVerilog (e.g., SV parser)

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License

GNU Library or Lesser General Public License version 2.0 (LGPLv2)

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2005-03-31

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