Driving interfaces on the negative edge does help avoid testbench-RTL race conditions for sampling and driving. But when RTL has instantiated clock gating cells (where the enable must be driven before the falling edge to be considered), driving the interface on the falling edge means that the verification may lead to incorrect results.
I learned that clocking blocks can be used to sample before the clock rising edge and to drive after it to avoid these race conditions. I am not sure if there are other ways to achieve driving and sampling at the rising edge.
I am a design engineer and am working on a design that will have multiple P-first-latch followed by AND gate integrated clock gates, some with interface signals.
I bet other design engineers that want to exercise their new or existing designs could use a good example framework that supports ICGs.
Anonymous
thanks ammon. it's a good idea. don't know when I'll get to it, but it's on my list. thanks for bringing it up.
-neil