Hi,
I'm using SVEditor together with CDT and other Eclipse plugins to work on a project with HDL code in SV, but also with C code. For C, we use a coding style with four spaces (pretty standard). In CDT, indenting with four spaces can be configured. However, for SystemVerilog we follow the (also pretty common) Emacs default of three space indentation. It would be nice if SVEditor had a setting to configure the indentation size just for SystemVerilog files. Using the Eclipse default of all editors requires us to change the global default to three spaces, which is wrong in any other file type than SV.
I've looked through the other bug reports and feature requests and didn't find this one yet, please apologize if I missed something.
Best,
Philipp