#415 Error in "SystemVerilog Project Properties"

[jeff zhang]

Hi,

I installed Eclipse 4.5.1, and sveditor 1.8.3
After i imported the example design chip1. I did "Click on System Verilog Project > Argument files> Add>Add Project Path Browse your way to chip1/sim/files.f".
Eclipse shows "The currently displayed page contains invalid values" in the "SystemVerilog Project Properties" page.
It seems variable CHIP is not created. I tried to created CHIP, i see the same problem.
I removed CHIP in the files.f, and moved files.f to the project root. It seems the sveditor parsed the design, but i still see the error in the "systemVerilog Project Properties" page.

Is my Eclipse not right version?

Thanks
Jeff

[StevenAZ]

Hi Jeff,

I am not able to replicate what you have shown. Does the message pop-up when you first click on the SystemVerilog Project item, or after you have hit "OK".

Did you recently upgrade from a previous version of SVE?

[StevenAZ]

Specifically, what step are you in in the tutorial when you get this error?

[jeff zhang]

Hi steven,

Thanks a lot for your reply.

It is a fresh installation.
using this tutorial http://sveditor.sourceforge.net/tutorial/sveditor_tutorial.html
In step 13 I selected files.f. Then I clicked ok in step 14. Then I see error as snapshot2.png shows. After this, if I want to go back "SystemVerilog Project Properties", i see error as snapshot3.png.

Thanks
Jiefan

[StevenAZ]

What operating system are you running on?

[jeff zhang]

It is Centos 7. Thanks

[Vinay Jain]

why perspective is set to JAVA EE? will you just try same after changing perspective to SVEdtior

[StevenAZ]

@Jeff

I think this may have been related to:
421 Eclipse Preference not importing correctly from preference file

Are you still seeing the issue?