[sigrok-devel] FPGA LA code status, and plans

[Iztok J. <izt...@gm...>]

Hi,

Ian Davis was probably not part of our previous conversation, here is a link
to the archive<http://sourceforge.net/mailarchive/forum.php?thread_name=CAAk4mkY9u%2B%3DuD_vZQRmDKs8fqZFrzoHrnBb4%2BY4pVjht%2BA-jYg%40mail.gmail.com&forum_name=sigrok-devel>
.

First I would like one owner of the logic sniffer hardware willing to test
my firmware builds to step forward. I will attach an image which kind of
should work the same as the original, external clock probably does not work
well. If the modified code works, I can continue at the current peace.
Otherwise I have to go back and rewrite the original test environment
first, so I have a proper reference to check against.

Also somebody could look into the PIC code and the USB code to start
thinking about generalizing those APIs too.

This is what I have done till now:
- recoded module port lists into the less redundant Verilog 2001 style
- moved almost all device specific code (clocking, IO) to the top level file
- rewrote memories into generic code, which compiles on all tools (I plan
to properly test this)
- replaced blocking assignment operators (used for combinatorial logic)
with non-blocking ones for all FlipFlops
- partially changed the coding style where the combinatorial logic is coded
in a sequential language style, not appropriate for RTL
- fixed a few instances of the reset signal being used conspiratorially
more remain in the trigger code, this cause non optimal code, Synplify will
complain about it
- changes the naming scheme of data streaming module ports, to more
closely resemble the standard
AXI4-Stream<http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.html>protocol,
which is supported by
Xilinx<http://www.xilinx.com/products/intellectual-property/axi4-stream_interconnect.htm>and
Altera SoC tools
- updated the bench code to use some SystemVerilog, I use Icarus Verilog
GIT for simulations
- generalized some code have a parameterized data width, currently it was
fixed to 32bits

After all this changes the FPGA should still be compatible with the
original code.

Here are the remaining tasks I have to go through, before I can start
changing the functionality:
1. write module level (sync, sample, trigger, align, rle, memory, SPI, ...)
tests which actually report success/failure of the test, currently a
developer knowing what to expect must look into the waves and logs
2. write top level tests with success/failure reports
3. fix remaining portability issues, mostly handling of reset and DDR
clocks (should be compatible with  most FPGA device families from Xilinx,
Altera, Lattice)
4. continue with the parameterization of the code, module level should be
tested with different parameter settings
5. just to catch more warnings compile the code using other synthesis tools
(Synplify, Vivado, Quartus)

With the next steps backwards compatibility will probably be lost:
1. generalize the memory interface, better separation between the write and
the read side is needed, all data transfers should be measured exclusively
in bytes, this will enable the use of plugable memory controllers accessing
fast and large external memories
2. recode the SPI interface, it is currently sampling the data and clock
inputs, and running the data shift register at the internal clock, to
achieve the full SPI speed the shifter should run directly on SPI clock,
clock domain crossing should be done on byte level
3. If I understood it correctly the order in which data is read out is the
opposite of what would be expected, I do not think it does make sense to
keep this for backwards compatibility anymore, since we control the host
software
4. some generalizations are needed for a plugable host interface to support
other boards (UART, SPI, FX2 compatible FIFO, I2C, JTAG), also the host can
be inside the FPGA on devices with integrated ARM CPU and memory
controllers (AMBA AXI4 for Cyclone
V<http://www.altera.com/devices/fpga/cyclone-v-fpgas/cyv-index.jsp>
 and Zynq-7000<http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm>
)

Regards,
Iztok Jeras