SLSignal_Prototype

• Searchlight Signal Prototype
  • Features
  • Track Diagram
  • Use Cases
    • Direction of Travel
    • Entering Trains
    • Exiting Trains
    • Crossovers
  • Block Diagram
  • Logic Overview
    • Single Turnout Module (STM)
    • Yard Ladder Module (YLM)
    • Putting It Together
  • Logic Equations
  • Hardware Implementation
    • Input Circuits
    • Core Logic
    • Output LED Drivers
    • Bill of Materials

Searchlight Signal Prototype

The prototype version of Searchlight Signal is a simple logic controller that uses DIP switches for turnout indication and simple logic embedded in a Programmable Logic Device (PLD) chip to determine the signal outputs. The system's logic is specifically designed around the staging yard portion of my model railroad layout.

Because the logic implemented is specific to the particular track arrangement and use case, this design as-is may not be applicable to other layouts. However, the basic design can be adapted by reworking the logic portion to suit the user's layout.

Inputs and logic are provided for accommodating Track Occupancy, but I do not plan to install the sensors on the layout at this time.

Why do this? What value add does the logic give vs. directly controlling the signals with individual switches? The logic links the turnout position to the signal indication such that operation is simpler for the user. One sets the (logic input) switch exactly the same way as the track switch. The only thinking required of the user is to correlate the track switch to its matching DIP. Plus, when the remote track switch control is implemented, the signal logic is automated by simply tying the track switch control directly to the signal logic, removing human intervention entirely.

Features

• 8 turnout indication inputs (DIP switches)
• 12 2-light Green/Red signal outputs
• 8 Track Occupancy inputs provided
• Dispatcher override turns any output red.
• Self-contained, reprogrammable design

Track Diagram

none | 600px

In the above drawing, the lines represent tracks. Turnouts are numbered 1-8, and signals are designated with letters A-M (omitting "I"). The tracks marked (EM) and (WM) are the main lines entering the yard, and the tracks marked (ES) and (WS) lead to off-layout staging.

For the prototype, each signal location (A-M) will have a 2-color-light (green/red) dwarf signal installed so as to be visible from a train approaching the associated turnout. Signal aspects will be derived from logic based on the following inputs:

• Turnout positions
• Track occupancy detection
• Dispatcher-assigned track direction-of-travel
• Dispatcher direct signal override

Because at the current stage of layout development all turnouts are under manual control - and to simplify the design of the controller, turnout positions will be indicated by a set of DIP switches on the logic board. This requires that the operator throw TWO switches - the actual turnout switch on the layout and the corresponding DIP switch on the control board - in order to properly set the signals. This is admittedly error-prone. Future versions of the controller will incorporate automatic turnout position sensing, eliminating this dependency.

Use Cases

The following rules describe the usage of the tracks.

Direction of Travel

In addition to the turnout/switch settings, each staging track must have a direction of travel assigned to it at any given time. This is a purely logical convention, assigned by the "dispatcher" (operator), but it prevents two trains from entering the same track in opposite directions.

Direction of travel is governed by an Eastbound/Westbound switch for each yard track, including two such switches for each half of Track 1. Direction of travel is similarly assigned to each of the two main lines and two external staging tracks.

Entering Trains

• Trains may enter Tracks 1-3 Eastbound from the West Main (WM) via Turnouts 8, 7, and 6.
• Trains may enter Tracks 1-3 Westbound from the East Main (EM) via Turnouts 1, 2, and 3.
• Trains may enter Track 1 Eastbound from the Mine Branch via Turnouts 4/5.
• Trains may enter Track 3 Eastbound/Westbound from External Staging (ES or WS) via Turnouts 3 and 6.

Exiting Trains

• Trains may exit Westbound to West Main (WM) via Turnouts 6, 7, and 8
• Trains may exit Eastbound to East Main (EM) via Turnouts 1, 2, and 3
• Trains may exit Westbound to Mine Branch via Turnouts 4/5
• Trains may exit Eastbound/Westbound to External Staging (ES or WS) via Turnouts 3 and 6.

Crossovers

Turnouts 2/3, 6/7, and 4/5 form crossover pairs, and should be switched in tandem. Because all switches are manual at this time, it is possible to switch them independently, and the signal logic must anticipate this possibility. When remote / power switch control is installed, these crossover pairs will be mated so that they cannot be operated independently.

Block Diagram

Here is a block diagram of the circuit as conceived.

none | 400px

All of the inputs to the controller can be from either on-board switches or external signals from turnout controllers or external panel-mount switches, or even from a computer, for example.

The signal outputs are designed to directly drive either green or red (or 3-wire bicolor) LEDs. The actual LED output connection scheme will be a separate 3-pin header for each signal. See below for the pinouts.

All of the "smarts" are contained within the ATF1504 CPLD, a programmable logic chip. The JTAG port shown at bottom is used to program the CPLD without removing it from the board. JTAG is an industry standard interface for testing and programming these types of chips.

Logic Overview

There are four basic input factors that affect the signal outputs of the controller:

• Turnout positions
• Track occupancy
• Dispatcher-designated track direction
• Dispatcher-controlled signal overrides

For our prototype staging location, this comprises 8 turnouts, 8 tracks, and 24 signal lights (12 signals * 2 lights). This is too many I/Os to consider discrete (7400-series) logic or simple PLDs (16V8, 22V10). We will be targeting a larger industry standard programmable logic device like the Atmel ATF1504, which comes in a 64-I/O package.

If we look closely at the track diagram, we realize that the East and West ends of the yard are symmetric, with 3 turnouts and 5 signals. Both sides have a mainline and a staging track entering the yard, and 3 yard tracks to manage. In the center is a much simpler crossover to the Mine Branch track.

To work out the logic, we will designate the tracks with the following names:

• EM : East Mainline
• WM : West Mainline
• ES : East off-layout Staging
• WS : West off-layout Staging
• MB : Mine Branch
• T1 : Track 1
• T2 : Track 2
• T3 : Track 3

When referencing the layout diagram, turnouts will be designated as "TOx", where x is 1-8 corresponding to the turnout number on the diagram. Signals will be designated with the letters shown in the drawing.

The overall system will be broken down into 3 instances of 2 basic components.

Single Turnout Module (STM)

The Single Turnout Module controls the two routes and 3 signals associated with a single turnout.

IO Map:

I/O Type Description Layout Map

TO
Input
Turnout position
TO4

DIR[0:2]
Input
Track Direction (Dispatch)
T1(East), T1(West), MB

OCC[0:2]
Input
Track Occupancy (sensor)
T1(East), T1(West), MB

SIG_OV[0:2]
Input
Dispatcher Signal Override
L, M, (unused)

SIG[0:2]
Output
Signal controls
L, M, (unused)

Internally, the logic progresses in three stages. First, the selected route through the turnout is detected. This is trivial for a single turnout, but for more complex trackwork is not. Second, the selected route is vetted for Dispatcher-selected direction and track occupancy. Third, the Dispatcher signal override is considered before calculating and driving the correct signal aspect for all 3 signals.

Yard Ladder Module (YLM)

The Yard Ladder Module (YLM) controls the signals for one end of the yard. Conceptually, it is identical to the STM, but handles more inputs and outputs.

IO Map:

I/O Type Description East Side Map West Side Map

TO[0:2]
Inputs
Turnout positions
TO1, TO2, TO3
TO8, TO7, TO6

DIR[0:4]
Inputs
Track Directions (Dispatch)
EM, T1, T2, T3, ES
WM, T1, T2, T3, WS

OCC[0:4]
Inputs
Track Occupancy (sensors)
EM, T1, T2, T3, ES
WM, T1, T2, T3, WS

SIG_OV[0:4]
Inputs
Dispatcher Signal Override
A, B, C, E, D
K, J, H, F, G

SIG[0:4]
Outputs
Signal controls
A, B, C, E, D
K, J, H, F, G

Internally, the logic process is identical to the STM, though the equations are somewhat more complex.

Putting It Together

To build the overall systems, we connect three modules - two YLMs and one STM within a master module. Due to the overall number of IOs, we'll use a larger PLD. The Atmel part mentioned above is available in single units for about $6.50, where a single 22V10 costs about $2.25 in small quantities. The 22V10 has plenty of internal logic, but nt enough IOs. Since we would need at least 2 and probably 3 22V10s, the cost is a minor issue.

The overall controller IO looks like this:

I/O Type Description Layout Map

TO[0:7]
Inputs
Turnout positions
TO1, TO2, TO3, TO4, TO5, TO6, TO7, TO8

DIR[0:7]
Inputs
Track Directions (Dispatch)
EM, T1, T2, T3, ES, WM, WS, MB

OCC[0:7]
Inputs
Track Occupancy (sensors)
EM, T1, T2, T3, ES, WM, WS, MB

SIG_OV[0:11]
Inputs
Dispatcher Signal Override
A, B, C, D, E, F, G, H, J, K, L, M

SIG[0:11]
Outputs
Signal controls
A, B, C, D, E, F, G, H, J, K, L, M

These are the connections at the chip pins. Internally, the signals get routed to/from all three modules (the 2 YLMs and the STM), which do the work.

Logic Equations

The logic for the PLD is written in a language called Verilog, which is a Hardware Description Language (HDL) used for this purpose (among many other things).

The Verilog files for the STM, YLM, and overall chip design will be available in the SVN tree.

Hardware Implementation

The controller will be implemented on an etched PCB with surface mount components where available. Inputs will be DIP switches, with provisions for external connections for turnout position and track sensing. Track direction and signal override are inherently human inputs, and will have provision for remote panel-mount switches.

Input Circuits

The input circuits are very simple. There are 4 input buses:

• TO [0:7] - the turnout position indications
  • '0' == Lined for main (straight through turnout, usually)
  • '1' == Diverging route (curved route, usually)
• OCC[0:7] - track occupancy
  • '0' == Track is clear
  • '1' == Track is occupied or obstructed
• DIR[0:7] - track direction (by convention specific to layout)
  • '0' - Entering the yard
  • '1' - Exiting the yard
• SIG_OV[0:11] - Red Signal override
  • '0' - Force RED or STOP aspect
  • '1' - Allow conditional signal aspect
• +5V DC Power (2.5mm barrel)

Note that the SIG_OV input may seem a little backward, but it allows the SIG_OV signal to be wired directly to the signal logic output without using any logic gates.

SIG_OV and DIR are human user (Dispatcher) inputs, and will be wired to either switches or computer inputs. The switches will be mounted on the board, but provision made for remote mounting.

TO and OCC are track condition sensing inputs, and could be connected directly to turnout motors or sensors on the track.

All inputs will be SPST DIP switches which will ground their respective input line when closed or allow a pull-up resistor to pull the line high when open. The DIP switches will be mounted on board, and will be backed up by 2-pin header strips for remote connection.

For the prototype, no isolation or signal conditioning will be provided. Therefore care must be taken that any remote connections provide appropriate signal conditioning for direct input into the 5V tolerant CMOS inputs of the ATF1504 core logic. In the future, specific provisions may be added for direct connection to different types of input circuits.

Caveat: Since I know that the plan for my personal layout is to use Tam Valley Depot Quad Servo Controllers for turnout control, I may include circuitry as necessary to allow direct connection from the Quad outputs to this board.

For the power input, a full power conversion and regulator circuit is envisioned, but the initial prototype version will likely have only a +5V DC input plug with some very basic filtering.

Core Logic

The core logic will be implemented in an Atmel ATF1504AS CPLD chip, for reasons explained above. The chip is powered at 5V, and (while capable of 3.3V I/O) will have 5V I/O as well. No clock circuitry will be provided, as the logic does not at this time require clocked registers.

If there is room on the board, I may add a crystal circuit for future expansion.

A 4-pin header for the JTAG in-circuit programming port will be provided.

Unused I/O pins will be brought out to a header for future expansion.

Wherever possible, the "regular" inputs and outputs to the circuit will be routed to the general-purpose IO pins, leaving the dual (or triple) purpose IOs free for future use in their special-purpose mode. It is fully anticipated that this board could be used for some alternate logic function, or easily modified for such use.

Output LED Drivers

The SIG[0:11] outputs from the core logic will be fed to a set of 7406 Inverting and 7407 Non-Inverting Open Collector Hex Driver chips (one inverting and one non-inverting for each SIG output). These will convert the High/Low Green/Red logic outputs into separate active low on/off outputs for each LED.

The output connector for each signal will be 3 wires (pinout TBD):

• +5V Supply
• Red LED Cathode
• Green LED Cathode

The Anodes of the LEDs should be connected through an external current limit resistor to the +5V pin.

The Red Cathode pin will be connected to the output of a 7407 Non-Inverting driver, so that when the logic output is low, the Red LED will be turned on.

The Green Cathode pin will be connected to the output of a 7406 Inverting driver, so that when the logic output is high, the driver output is low and the Green LED will be turned on.

Note that at no time (except the transient) are both outputs active.

The 7406/7407 drivers allow up to 40mA current per output, which should be more than sufficient for the targeted LEDs.

Bill of Materials

Item Name Description Qty Unit Price Net Price Notes

1
CPLD
Atmel ATF1504
1
$6.13
$6.13
Atmel ATF1504AS-10-JC84

2
Red LED Driver
74LS07DR-SOIC14
2
$0.77
$1.54

3
Green LED Driver
74LS06DR-SOIC14
2
$0.97
$1.94

4
Input Pullup Resistors
SMT Bussed RPAK
3
$1.24
$3.72
CTS 767-141-103GP or equiv.

5
TO, OCC, DIR Switches
8-pin DIP switch
3
$1.74
$5.22
Tyco 3-5435640-9 or equiv.

6
SIG_OV Switch
12-pin DIP switch
1
$2.43
$2.43
Tyco 3-5435640-2 or equiv.

7
TO, OCC, DIR Headers
8x2-pin Header
3
$5.43
$16.29
Tyco 87215-5 or equiv.

8
SIG_OV Header
12x2-pin Header
1
$8.82
$8.82
Tyco 87215-8 or equiv.

9
LED Connectors
4x3 Pin Header
3
$0.90
$2.70
Tyco 829492-4 or equiv.

10
JTAG Port
4x1 Pin Header
1
$1.44
$1.44
Tyco 87224-4 or equiv.

11
Power Input
2.5mm Barrel Conn.
1
$1.44
$1.44
Switchcraft RAPC712X or similar

12
Power Regulator
Design TBD
1
 ???
 ???

13
PCB Setup Fee
1
$25.00
$25.00

14
PCB
1
$36.00
$36.00
Estimated 12in^2 @ $3/in^2

Ancillary passives are not (yet) listed.

Unit cost is $26.56, not counting the PCB, power regulation circuit, and remote input headers (items #7 & #8).