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Rabbits

Philipp Klaus Krause

Rabbits

There are several revisions of the Z80-based Rabbit microcontrollers. A major difference is the addition of 16-bit mode with additional registers in the Rabbit 4000. Also, there are a number of bugs relevant to SDCC that got fixed in later revisions.
Currently, SDCC has the r2k, r2ka and r3ka backends.

Instruction sets

r2k, r3ka, r4k, r6k.

The Rabbit 4000 and Rabbit 5000 have 4 modes, set via 2 bits in the internal I/O register EDMR. The pages ed, fd, dd and cb pages are the same in all modes. The 6d page is the same in all modes that have it.
00 - "Default instruction set" / "Rabbit 3000 mode" - binary compatible with Rabbit 2000 and Rabbit 3000A.
11 - "Enhanced instruction set" - assembler compatible with Rabbit 2000 and Rabbit 3000A, but different opcodes. Has 6d and 7f pages. Many instructions removed from main page, most of them replaced by new instructions. The 7f page contains instructions that would be on the main page in mode 00, but have been replaced by new instructions.
01 - Undocumented. ld l, l instruction removed from main page, new 6d page added. Otherwise the same as 00.
10 - Undocumented. ld l, l and ld a,a instructions removed from main page, new 6d and 7f pages added. The 7f page contains the instructions that would be on the main page in mode 11, but not mode 00.

Bugs

Bug r2k r2ka r2kb r2kc r3k r3ka r4k r5k r6k
ioi / ioe prefix bug x
ddcb / fdcb wait state bug U
conditional jump wait state bug U
ldir / lddr wait state bug U
mul wait state bug w
ldir / lddr split bug S
new ldir / lddr wait state bug w w w w w
16-bit mode alignment bug X
ioi / ioe bit bug X
ret cc bug X
rmw wait state bug W W W W W W W W

Legend:
x s w u - bug present, worked around by SDCC
X S W U - bug present, not worked around by SDCC
w W u U - wait state bug, only relevant when the Rabbit is configured to have wait states for some memory.
s S - instruction / data split bug, only relevant when instruction / data split is enabled, which is currently not supported by SDCC.
u U - bug can be worked around by the user by configuring memory that needs wait states to use one additional wait state.
The 16-bit mode alignment bug only affects 16-bit mode, which is not currently supported by SDCC.
The rmw wait state bug also is only relevant when executing fast code writing to slow memory, such as code in fast RAM writing to slow battery-backed SRAM.


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