Re: [sdcc-devel] ROM and EEPROM in XDATA

[Daniel D. <dr...@ma...>]

On 14 Dec 2001, Russel Winder wrote:

> Our real need is to remove the necessity to have the XDATA
> initialization code for parts of XDATA that are ROM and for the
> simulator to allow the address spaces to be partitioned by type of
> memory.

I think first we should make it clear what we think when talking about
"XDATA, CODE" and "ROM, RAM" and "address space" and "memory type".

In mcs51 there are two different way to access axternal memory (we can
skip internal ram and sfr, becouse there is no problem with them):

1. fetch, movc
2. movx

Both type of memory access can use address range 0..64k. Because of
different "read" signals, it is possible to use different physical
memory outside of the chip for these two different access types. So,
address ranges of access types can overlap.

Application programs can have code part and data part. Code part is
usualy accessed by memory access type 1 (let's say MAT1). Data part is
usualy accessed by MAT2. But it is not strict rule. If read signals of
the memories are hacked, it is possible to access code part by MAT2
and data part by MAT1...

Simulator use two 64k size byte arrays to simulate memories for MAT1
and MAT2, let's say they are M1 and M2. In real world they can be ROM,
RAM, EEPROM, etc, but in simulated world they are just two arrays, so
they can be written and read (with `set mem' command for example)
which means that both memories are RAM!

I think we can say that memory address space is eq with

- memory access type, and
- the memory accessed by it.

Let's call MAT1 as CODE address space and call MAT2 as XRAM address
space. Simulator use M1 for CODE and M2 for XRAM.

I'm planing to implement "mapping" or "redirection" in the simulator,
which means it will be possible to say

"use M2 instead of M1 for MAT1 if address=x..y"

I hope it can cover some "strange" real situations. Using mapping
address ranges could be assigned to access types, like

  0 ...  4k   MAT1 (CODE) (mat2 redirected to m1)
 4k ... 32k   MAT2 (XRAM) (mat1 redirected to m2)
32k ... 48k   MAT1 (CODE) (mat2 redirected to m1)
48k ... 64k   MAT1 and MAT2 (CODE & XRAM) (no redirection)

Daniel