Re: [Sdcc-user] r/w order for STM8 16b registers

[Philipp K. K. <pk...@sp...>]

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On 18.04.2014 09:49, Maarten Brock wrote:
> Hello Georg,
> 
> Is this behaviour true for all 16 bit SFR's? Or is it different for
> every other SFR? If it's always the same then maybe SDCC could take
> this into account.
> 
> Maarten
> 
>> hi all,
>> 
>> it might be common knowledge in the community, but it sure was
>> new to me (and took me some time to debug)…
>> 
>> As you know the STM8 is and 8-bit uC, so reading from or writing
>> to 16b peripheral registers (SFR) takes place in 2 steps. And I
>> found that the sequence of access matters for 16b peripheral
>> registers (SFR), and is different for read and write: write:
>> byteH+byteL is ok, but byteL+byteH (or word write in C) fails 
>> read: byteL+byteH (and word read in C) is ok, but byteH+byteL
>> fails
>> 
>> I observed this behavior for SDCC v3.4 RC2, and also for Cosmic
>> C-compiler 4.3.7. Hope this note helps avoiding bugs, and saving
>> debugging time.

For which sfrs did you test?

>> Have a nice day,  :-) Georg
> 

Unfortunately, AFAIK, this is not the same for all 16-bit sfrs.

In particular, some of the timer-related registers we always need to
access the high byte first, followed by the low byte (both on reads
and write):

Examples from the STM8L101:

For the TIM_CNTR register, the high byte must be read first, followed
by the low byte.

For the TIM_AAR register, the high byte must be written first,
followed by the low byte.

But I think it is only the timer registers that are high byte first.

Philipp

P.S.: If we can, we often want to read / write the low byte first,
since ldw is faster than to ld, and ldw reads / writes the low byte first.

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