#2628 fetchLitPair overwrites live IY register

[Carlos Sánchez de La Lama]

In the attached test case, both "e->p = data" assigments (lines 14 and 23) generate wrong code. Address of "e->p" is cached into register IY, but fetchLitPair overwrites it when trying to load the address of "data" variable.

;sdcc_bug.c:23: e->p = data;

        ld      iy, #_data
        ld      a, 0 (iy)
        ld      0 (iy), a
        ld      a, 1 (iy)
        ld      1 (iy), a

If I add "--oldralloc" or "--reserve-regs-iy" options, code generated looks correct.

Live ranges of symbols in generated iCode seem to be ok, "e->p" is named iTemp1 in iCode dump and is live since the end of the function, and when checked against 0 in source line 14 it gets cached into IY. But when "genAssign (pointer)" later calls fetchLitPair to emit "e->p = data" assignment, overwrites the live IY.

Compilation command line is:
sdcc -mz80 -S -o sdcc_bug.asm sdcc_bug.c
sdcc -mz80 --i-code-in-asm --fverbose-asm -S -o sdcc_bug_verbose.asm sdcc_bug.c

SDCC version information:
sdcc --version
SDCC : mcs51/z80/z180/r2k/r3ka/gbz80/tlcs90/ds390/TININative/ds400/hc08/s08/stm8 3.6.8 #9946 (Linux)
published under GNU General Public License (GPL)

[Carlos Sánchez de La Lama]

I have created a regression test case (attached). As expected, being a codegen problem, the case passes in other targets (I have tested in on mcs51-small) but fails on ucz80.

[Philipp Klaus Krause]

Fixed in [r9947].

Philipp