Re: [Sbcl-devel] [PATCH] x86-64 optimizations

[Vitaly M. <v.m...@gm...>]

At Mon, 18 May 2009 16:55:16 -0400, Nathan Froyd wrote:

> These are a nice idea; did you check that they're not slowing down the
> (+ <fixnum> <fixnum>) case?

It does :(

>  Because the lower cost is going to
> indicate to the compiler that those VOPs are better for fixnum/fixnum
> addition, which is going to pessimize a lot of code unnecessarily.

I'm not too much familiar with SBCL internals, but I suspect SBCL
doesn't take in count MOVE-WORDs. Therefore it decides to generate

; 029B5B3B:       488BC7           MOV RAX, RDI               ; no-arg-parsing entry point
;       3E:       48C1F803         SAR RAX, 3
;       42:       488D14C3         LEA RDX, [RBX+RAX*8]

instead of one LEA for fixnums in your foo example.

If I'm correct, SBCL will never do the right choice.

-- 
wbr, Vitaly