[Sbcl-commits] CVS: sbcl/src/compiler/x86-64 macros.lisp,1.11,1.12 vm.lisp,1.6,1.7

[Juho S. <js...@us...>]

Update of /cvsroot/sbcl/sbcl/src/compiler/x86-64
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv6126/src/compiler/x86-64

Modified Files:
	macros.lisp vm.lisp 
Log Message:
0.9.6.14:
	Faster allocation on x86-64 (25% speedup on memory-intensive 
        CL-BENCH tests, 5% on more generic stuff like COMPILER):
        * Inline allocation was using a memory-to-register XCHG
          (latency 16 on Athlon 64) on the fast path. Use a temporary
          register instead.
        * Change the temp-tn from r13 to r11, which has a shorter
          encoding (results in smaller core and better icache behaviour)

	TODO: Check whether the XCHG issue also caused the bizarre P4
        performance problems with the (disabled) x86 inline
        allocation support, and whether anything can be done to fix the
        problem. Using the same solution is probably impossible due to
        the lack of extra registers.


Index: macros.lisp
===================================================================
RCS file: /cvsroot/sbcl/sbcl/src/compiler/x86-64/macros.lisp,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- macros.lisp	26 Aug 2005 22:16:47 -0000	1.11
+++ macros.lisp	3 Nov 2005 12:41:07 -0000	1.12
@@ -130,9 +130,9 @@
 (defun allocation-tramp (alloc-tn size &optional ignored)
   (declare (ignore ignored))
   (inst push size)
-  (inst lea r13-tn (make-ea :qword
+  (inst lea temp-reg-tn (make-ea :qword
                             :disp (make-fixup "alloc_tramp" :foreign)))
-  (inst call r13-tn)
+  (inst call temp-reg-tn)
   (inst pop alloc-tn)
   (values))
 
@@ -168,12 +168,14 @@
     (cond (in-elsewhere
            (allocation-tramp alloc-tn size))
           (t
+           (inst mov temp-reg-tn free-pointer)
            (unless (and (tn-p size) (location= alloc-tn size))
              (inst mov alloc-tn size))
-           (inst add alloc-tn free-pointer)
+           (inst add alloc-tn temp-reg-tn)
            (inst cmp end-addr alloc-tn)
            (inst jmp :be NOT-INLINE)
-           (inst xchg free-pointer alloc-tn)
+           (inst mov free-pointer alloc-tn)
+           (inst mov alloc-tn temp-reg-tn)
            (emit-label DONE)
            (assemble (*elsewhere*)
              (emit-label NOT-INLINE)
@@ -189,9 +191,9 @@
 (defun allocation (alloc-tn size &optional ignored)
   (declare (ignore ignored))
   (inst push size)
-  (inst lea r13-tn (make-ea :qword
+  (inst lea temp-reg-tn (make-ea :qword
                             :disp (make-fixup "alloc_tramp" :foreign)))
-  (inst call r13-tn)
+  (inst call temp-reg-tn)
   (inst pop alloc-tn)
   (values))
 

Index: vm.lisp
===================================================================
RCS file: /cvsroot/sbcl/sbcl/src/compiler/x86-64/vm.lisp,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- vm.lisp	14 Jul 2005 19:13:49 -0000	1.6
+++ vm.lisp	3 Nov 2005 12:41:07 -0000	1.7
@@ -71,7 +71,7 @@
   (defreg r15b 30 :byte)
   (defregset *byte-regs*
       al cl dl bl sil dil r8b r9b r10b
-      r11b #+nil r12b #+nil r13b r14b r15b)
+      #+nil r11b #+nil r12b r13b r14b r15b)
 
   ;; word registers
   (defreg ax 0 :word)
@@ -116,8 +116,13 @@
   ;; list of qword registers.  However
   ;; <jsnell> r13 is already used as temporary [#lisp irc 2005/01/30]
   ;; and we're now going to use r12 for the struct thread*
+  ;;
+  ;; Except that now we use r11 instead of r13 as the temporary,
+  ;; since it's got a more compact encoding than r13, and experimentally
+  ;; the temporary gets used more than the other registers that are never
+  ;; wired. -- JES, 2005-11-02
   (defregset *qword-regs* rax rcx rdx rbx rsi rdi
-             r8 r9 r10 r11      r14 r15)
+             r8 r9 r10 #+nil r11 #+nil r12 r13  r14 r15)
 
   ;; floating point registers
   (defreg float0 0 :float)
@@ -382,15 +387,20 @@
                       `(progn ,@(forms)))))
 
   (def-misc-reg-tns unsigned-reg rax rbx rcx rdx rbp rsp rdi rsi
-                    r8 r9 r10 r11  r12 r13 r14 r15)
+                    r8 r9 r10 r11 r12 r13 r14 r15)
   (def-misc-reg-tns dword-reg eax ebx ecx edx ebp esp edi esi)
   (def-misc-reg-tns word-reg ax bx cx dx bp sp di si)
   (def-misc-reg-tns byte-reg al cl dl bl sil dil r8b r9b r10b
-                    r11b r14b r15b)
+                    r11b r12b r13b r14b r15b)
   (def-misc-reg-tns single-reg
       float0 float1 float2 float3 float4 float5 float6 float7
       float8 float9 float10 float11 float12 float13 float14 float15))
 
+;; A register that's never used by the code generator, and can therefore
+;; be used as an assembly temporary in cases where a VOP :TEMPORARY can't
+;; be used.
+(defparameter temp-reg-tn r11-tn)
+
 ;;; TNs for registers used to pass arguments
 (defparameter *register-arg-tns*
   (mapcar (lambda (register-arg-name)